Transmitting apparatus and interleaving method thereof

ABSTRACT

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No. 14/716,093 filed May 19, 2015, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field

Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes and transmits data, and an interleaving method thereof.

2. Description of the Related Art

In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, multi-channel, wideband, and high quality. In particular, as high quality digital televisions, portable multimedia players and portable broadcasting equipment are increasingly used in recent years, there is an increasing demand for methods for supporting various receiving methods of digital broadcasting services.

In order to meet such demand, standard groups are establishing various standards and are providing a variety of services to satisfy users' needs. Therefore, there is a need for a method for providing improved services to users with high decoding and receiving performance.

SUMMARY

Exemplary embodiments of the inventive concept may overcome the above disadvantages and other disadvantages not described above. However, it is understood that the exemplary embodiment are not required to overcome the disadvantages described above, and may not overcome any of the problems described above.

The exemplary embodiments provide a transmitting apparatus which can map a bit included in a predetermined bit group from among a plurality of bit groups of a low density parity check (LDPC) codeword onto a predetermined bit of a modulation symbol, and transmit the bit, and an interleaving method thereof.

According to an aspect of an exemplary embodiment, there is provided a transmitting apparatus including: an encoder configured to generate an LDPC codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Each of the plurality of bit groups may be formed of M number of bits. M may be a common divisor of N_(ldpc) and K_(ldpc) and may be determined to satisfy Q_(ldpc)=(N_(ldpc)−K_(ldpc))/M. In this case, Q_(ldpc) may be a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, N_(ldpc) may be a length of the LDPC codeword, and K_(ldpc) may be a length of information word bits of the LDPC codeword.

The interleaver may include: a parity interleaver configured to interleave parity bits of the LDPC codeword; a group interleaver configured to divide the parity-interleaved LDPC codeword by the plurality of bit groups and rearrange an order of the plurality of bit groups in bit group wise; and a block interleaver configured to interleave the plurality of bit groups the order of which is rearranged.

The group interleaver may be configured to rearrange the order of the plurality of bit groups in bit group wise by using the following equation:

Y _(j) =X _(π(j))(0≦j<N _(group))

where X_(j) is a j^(th) bit group before the plurality of bit groups are interleaved, Y_(j) is a j^(th) bit group after the plurality of bit groups are interleaved, N_(group) is a total number of the plurality of bit groups, and π(j) is a parameter indicating an interleaving order.

Here, π(j) may be determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.

When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 6/15, π(j) may be defined as in table 17.

The block interleaver may be configured to interleave by writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

The block interleaver may be configured to serially write, in the plurality of columns, at least some bit groups which are writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then divide and write the other bit groups in an area which remains after the at least some bit groups are written in the plurality of columns in bit group wise.

According to an aspect of another exemplary embodiment, there is provided an interleaving method of a transmitting apparatus, including: generating an LDPC codeword by LDPC encoding based on a parity check matrix; interleaving the LDPC codeword; and mapping the interleaved LDPC codeword onto a modulation symbol, wherein the mapping comprises mapping a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Each of the plurality of bit groups may be formed of M number of bits, and M may be a common divisor of N_(ldpc) and K_(ldpc) and may be determined to satisfy Q_(ldpc)=(N_(ldpc)−K_(ldpc))/M. In this case, Q_(ldpc) may be a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, N_(ldpc) may be a length of the LDPC codeword, and K_(ldpc) may be a length of information word bits of the LDPC codeword.

The interleaving may include: interleaving parity bits of the LDPC codeword; dividing the parity-interleaved LDPC codeword by the plurality of bit groups and rearranging an order of the plurality of bit groups in bit group wise; and interleaving the plurality of bit groups the order of which is rearranged.

The rearranging in bit group wise may include rearranging the order of the plurality of bit groups in bit group wise by using the following equation:

Y _(j) =X _(π(j))(0≦j<N _(group)),

where X_(j) is a j^(th) bit group before the plurality of bit groups are interleaved, Y_(j) is a j^(th) bit group after the plurality of bit groups are interleaved, N_(group) is a total number of the plurality of bit groups, and π(j) is a parameter indicating an interleaving order.

Here, π(j) may be determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.

When the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 6/15, π(j) may be defined as in table 17.

The interleaving the plurality of bit groups may include interleaving by writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

The interleaving the plurality of bit groups may include serially writing, in the plurality of columns, at least some bit groups which are writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then dividing and writing the other bit groups in an area which remains after the at least some bit groups are written in the plurality of columns in bit group wise.

According to various exemplary embodiments, improved decoding and receiving performance can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or other aspects will be more apparent by describing in detail exemplary embodiments, with reference to the accompanying drawings, in which:

FIGS. 1A to 12 are views to illustrate a transmitting apparatus according to exemplary embodiments;

FIGS. 13 to 18 are views to illustrate a receiving apparatus according to exemplary embodiments;

FIG. 19 is a block diagram to illustrate a configuration of a transmitting apparatus, according to an exemplary embodiment;

FIGS. 20 to 22 are views to illustrate a configuration of a parity check matrix, according to exemplary embodiments;

FIG. 23 is a block diagram to illustrate a configuration of an interleaver, according to an exemplary embodiment;

FIGS. 24 to 26 are views to illustrate an interleaving method, according to exemplary embodiments;

FIGS. 27 to 32 are views to illustrate an interleaving method of a block interleaver, according to exemplary embodiments;

FIG. 33 is a view to illustrate an operation of a demultiplexer, according to an exemplary embodiment;

FIGS. 34 and 35 are views to illustrate a method for designing an interleaving pattern, according to exemplary embodiments;

FIG. 36 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment;

FIG. 37 is a block diagram to illustrate a configuration of a deinterleaver, according to an exemplary embodiment;

FIG. 38 is a view to illustrate a deinterleaving method of a block deinterleaver, according to an exemplary embodiment;

FIG. 39 is a flowchart to illustrate an interleaving method, according to an exemplary embodiment;

FIG. 40 is a block diagram illustrating a configuration of a receiving apparatus according to an exemplary embodiment;

FIG. 41 is a block diagram illustrating a demodulator according to an exemplary embodiment; and

FIG. 42 is a flowchart provided to illustrate an operation of a receiving apparatus from a moment when a user selects a service until the selected service is reproduced, according to an exemplary embodiment.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Hereinafter, various exemplary embodiments will be described in greater detail with reference to the accompanying drawings.

In the following description, same reference numerals are used for the same elements when they are depicted in different drawings. The matters defined in the description, such as detailed construction and elements, are provided to assist in a comprehensive understanding of the exemplary embodiments. Thus, it is apparent that the exemplary embodiments can be carried out without those specifically defined matters. Also, functions or elements known in the related art are not described in detail since they would obscure the exemplary embodiments with unnecessary detail.

FIG. 1A is provided to explain transmitting apparatus according to an exemplary embodiment.

According to FIG. 1A, a transmitting apparatus 10000 according to an exemplary embodiment may include an Input Formatting Block (or part) 11000, 11000-1, a BIT Interleaved and Coded Modulation (BICM) block 12000, 12000-1, a Framing/Interleaving block 13000, 13000-1 and a Waveform Generation block 14000, 14000-1.

The transmitting apparatus 10000 according to an exemplary embodiment illustrated in FIG. 1A includes normative blocks shown by solid lines and informative blocks shown by dotted lines. Here, the blocks shown by solid lines are normal blocks, and the blocks shown by dotted lines are blocks which may be used when implementing an informative MIMO.

The Input Formatting block 11000, 11000-1 generates a baseband frame (BBFRAME) from an input stream of data to be serviced. Herein, the input stream may be a transport stream (TS), Internet protocol (IP) stream, a generic stream (GS), a generic stream encapsulation (GSE), etc.

The BICM block 12000, 12000-1 determines a forward error correction (FEC) coding rate and a constellation order depending on a region where the data to be serviced will be transmitted (e.g., a fixed PHY frame or mobile PHY frame), and then, performs encoding. Signaling information on the data to be serviced may be encoded through a separate BICM encoder (not illustrated) or encoded by sharing the BICM encoder 12000, 12000-1 with the data to be serviced, depending on a system implementation.

The Framing/Interleaving block 13000, 13000-1 combines time interleaved data with signaling information to generate a transmission frame.

The Waveform Generation block 14000, 14000-1 generates an OFDM signal in the time domain on the generated transmission frame, modulates the generated OFDM signal to a radio frequency (RF) signal and transmits the modulated RF signal to a receiver.

FIGS. 1B and 1C are provided to explain methods of multiplexing according to an exemplary embodiment.

FIG. 1B illustrates a block diagram to implement a Time Division Multiplexing according to an exemplary embodiment.

In the TDM system architecture, there are four main blocks (or parts): the Input Formatting block 11000, the BICM block 12000, the Framing/Interleaving block 13000, and the Waveform Generation block 14000.

Data is input and formatted in the Input Formatting block, and forward error correction applied and mapped to constellations in the BICM block 12000. Interleaving, both time and frequency, and frame creation done in the Framing/Interleaving block 13000. Subsequently, the output waveform is created in the Waveform Generation block 14000.

FIG. 2B illustrates a block diagram to implement a Layered Division Multiplexing (LDM) according to another exemplary embodiment.

In the LDM system architecture, there are several different blocks compared with the TDM system architecture. Specifically, there are two separate Input Formatting blocks 11000, 11000-1 and BICM blocks 12000, 12000-1, one for each of the layers in LDM. These are combined before the Framing/Interleaving block 13000 in the LDM Injection block. The Waveform Generation block 14000 is similar to TDM.

FIG. 2 is a block diagram which illustrates detailed configuration of the Input Formatting block illustrated in FIG. 1A.

As illustrated in FIG. 2, the Input Formatting block 11000 consists of three blocks which control packets distributed into PLPs. Specifically, the Input Formatting block 11000 includes a packet encapsulation and compression block 11100, a baseband framing block 11200 and a scheduler block 11300.

Input data packets input to the Input Formatting block 11000 can consist of various types, but at the encapsulation operation these different types of packets become generic packets which configure baseband frames. Here, the format of generic packets is variable. It is possible to easily extract the length of the generic packet from the packet itself without additional information. The maximum length of the generic packet is 64 kB. The maximum length of the generic packet, including header, is four bytes. Generic packets must be of integer byte length.

The scheduler 11200 receives an input stream of encapsulated generic packets and forms them into physical layer pipes (PLPs), in the form of baseband frames. In the above-mentioned TDM system there may be only one PLP, called single PLP or S-PLP, or there may be multiple PLPs, called M-PLP. One service cannot use more than four PLPs. In the case of an LDM system consisting of two layers, two PLPs are used, one for each layer.

The scheduler 11200 receives encapsulated input packet streams and directs how these packets are allocated to physical layer resources. Specifically, the scheduler 11200 directs how the baseband framing block will output baseband frames.

The functional assets of the Scheduler 11200 are defined by data size(s) and time(s). The physical layer can deliver portions of data at these discrete times. The scheduler 11200 uses the inputs and information including encapsulated data packets, quality of service metadata for the encapsulated data packets, a system buffer model, constraints and configuration from system management, and creates a conforming solution in terms of configuration of the physical layer parameters. The corresponding solution is subject to the configuration and control parameters and the aggregate spectrum available.

Meanwhile, the operation of the Scheduler 11200 is constrained by combination of dynamic, quasi-static, and static configurations. The definition of these constraints is left to implementation.

In addition, for each service a maximum of four PLPs shall be used. Multiple services consisting of multiple time interleaving blocks may be constructed, up to a total maximum of 64 PLPs for bandwidths of 6, 7 or 8 MHz. The baseband framing block 11300, as illustrated in FIG. 3A, consists of three blocks, baseband frame construction 3100, 3100-1, . . . 3100-n, baseband frame header construction block 3200, 3200-1, . . . 3200-n, and the baseband frame scrambling block 3300, 3300-1, . . . 3300-n. In a M-PLP operation, the baseband framing block creates multiple PLPs as necessary.

A baseband frame 3500, as illustrated in FIG. 3B, consists of a baseband frame header 3500-1 and payload 3500-2 consisting of generic packets. Baseband frames have fixed length K_(payload). Generic packets 3610-3650 shall be mapped to baseband frames 3500 in order. If generic packets 3610-3650 do not completely fit within a baseband frame, packets are split between the current baseband frame and the next baseband frame. Packet splits shall be in byte units only.

The baseband frame header construction block 3200, 3200-1, . . . 3200-n configures the baseband frame header. The baseband frame header 3500-1, as illustrated in FIG. 3B, is composed of three parts, including the base header 3710, the optional header (or option field 3720) and the extension field 3730. Here, the base header 3710 appears in every baseband frame, and the optional header 3720 and the extension field 3730 may not be present in every time.

The main feature of the base header 3710 is to provide a pointer including an offset value in bytes as an initiation of the next generic packet within the baseband frame. When the generic packet initiates the baseband frame, the pointer value becomes zero. If there is no generic packet which is initiated within the baseband frame, the pointer value is 8191, and a 2-byte base header may be used.

The extension field (or extension header) 3730 may be used later, for example, for the baseband frame packet counter, baseband frame time stamping, and additional signaling, etc.

The baseband frame scrambling block 3300, 3300-1, . . . 3300-n scrambles the baseband frame.

In order to ensure that the payload data when mapped to constellations does not always map to the same point, such as when the payload mapped to constellations consists of a repetitive sequence, the payload data shall always be scrambled before forward error correction encoding.

The scrambling sequences shall be generated by a 16-bit shift register that has 9 feedback taps. Eight of the shift register outputs are selected as a fixed randomizing byte, where each bit from t his byte is used to individually XOR the corresponding input data. The data bits are XORed MSB to MSB and so on until LSB to LSB. The generator polynomial is G(x)=1+X+X³+X⁶+X⁷+X¹¹+X¹²+X¹³+X¹⁶.

FIG. 4 illustrates a shift register of a PRBS encoder for scrambling a baseband according to an exemplary embodiment, wherein loading of the sequence into the PRBS register, as illustrated in FIG. 4 and shall be initiated at the start of every baseband frame.

FIG. 5 is a block diagram provided to explain detailed configuration of the BICM block illustrated in FIG. 1A.

As illustrated in FIG. 5, the BICM block includes the FEC block 14100, 14100-1, . . . , 14100-n, Bit Interleaver block 14200, 14200-1, . . . , 14200-n and Mapper blocks 14300, 14300-1, . . . , 14300-n.

The input to the FEC block 1400, 14100-1, . . . , 14100-n is a Baseband frame, of length K_(payload), and the output from the FEC block is a FEC frame. The FEC block 14100, 14100-1, . . . , 14100-n is implemented by concatenation of an outer code and an innter code with the information part. The FEC frame has length N_(inner). There are two different lengths of LDPC code defined: N_(inner)=64800 bits and N_(inner)=16200 bits

The outer code is realized as one of either Bose, Ray-Chaudhuri and Hocquenghem (BCH) outer code, a Cyclic Redundancy Check (CRC) or other code. The inner code is realized as a Low Density Parity Check (LDPC) code. Both BCH and LDPC FEC codes are systematic codes where the information part I contained within the codeword. The resulting codeword is thus a concatenation of information or payload part, BCH or CRC parities and LDPC parities, as shown in FIG. 6A.

The use of LDPC code is mandatory and is used to provide the redundancy needed for the code detection. There are two different LDPC structures that are defined, these are called Type A and Type B. Type A has a code structure that shows better performance at low code rates while Type B code structure shows better performance at high code rates. In general N_(inner)=64800 bit codes are expected to be employed. However, for applications where latency is critical, or a simpler encoder/decoder structure is preferred, N_(inner)=16200 bit codes may also be used.

The outer code and CRC consist of adding M_(outer) bits to the input baseband frame. The outer BCH code is used to lower the inherent LDPC error floor by correcting a predefined number of bit errors. When using BCH codes the length of M outer is 192 bits (N_(inner)=64800 bit codes) and 168 bits (for N_(inner)=16200 bit codes). When using CRC the length of M_(outer) is 32 bits. When neither BCH nor CRC are used the length of M_(outer) is zero. The outer code may be omitted if it is determined that the error correcting capability of the inner code is sufficient for the application. When there is no outer code the structure of the FEC frame is as shown in FIG. 6B.

FIG. 7 is a block diagram provided to explain detailed configuration of the Bit Interleaver block illustrated in FIG. 6.

The LDPC codeword of the LDPC encoder, i.e., a FEC Frame, shall be bit interleaved by a Bit Interleaver block 14200. The Bit Interleaver block 14200 includes a parity interleaver 14210, a group-wise interleaver 14220 and a block interleaver 14230. Here, the parity interleaver is not used for Type A and is only used for Type B codes.

The parity interleaver 14210 converts the staircase structure of the parity-part of the LDPC parity-check matrix into a quasi-cyclic structure similar to the information-part of the matrix.

Meanwhile, the parity interleaved LDPC coded bits are split into N_(group)=N_(inner)/360 bit groups, and the group-wise interleaver 14220 rearranges the bit groups.

The block interleaver 14230 block interleaves the group-wise interleaved LDPC codeword.

Specifically, the block interleaver 14230 divides a plurality of columns into part 1 and part 2 based on the number of columns of the block interleaver 14230 and the number of bits of the bit groups. In addition, the block interleaver 14230 writes the bits into each column configuring part 1 column wise, and subsequently writes the bits into each column configuring part 2 column wise, and then reads out row wise the bits written in each column.

In this case, the bits constituting the bit groups in the part 1 may be written into the same column, and the bits constituting the bit groups in the part 2 may be written into at least two columns.

Back to FIG. 5, the Mapper block 14300, 14300-1, . . . , 14300-n maps FEC encoded and bit interleaved bits to complex valued quadrature amplitude modulation (QAM) constellation points. For the highest robustness level, quaternary phase shift keying (QPSK) is used. For higher order constellations (16-QAM up to 4096-QAM), non-uniform constellations are defined and the constellations are customized for each code rate.

Each FEC frame shall be mapped to a FEC block by first de-multiplexing the input bits into parallel data cell words and then mapping these cell words into constellation values.

FIG. 8 is a block diagram provided to explain detailed configuration of a Framing/Interleaving block illustrated in FIG. 1A.

As illustrated in FIG. 8, the Framing/Interleaving block 14300 includes a time interleaving block 14310, a framing block 14320 and a frequency interleaving block 14330.

The input to the time interleaving block 14310 and the framing block 14320 may consist of M-PLPs however the output of the framing block 14320 is OFDM symbols, which are arranged in frames. The frequency interleaver included in the frequency interleaving block 14330 operates an OFDM symbols.

The time interleaver (TI) configuration included in the time interleaving block 14310 depends on the number of PLPs used. When there is only a single PLP or when LDM is used, a sheer convolutional interleaver is used, while for multiple PLP a hybrid interleaver consisting of a cell interleaver, a block interleaver and a convolutional interleaver is used. The input to the time interleaving block 14310 is a stream of cells output from the mapper block (FIG. 5, 14300, 14300-1, . . . , 14300-n), and the output of the time interleaving block 14310 is also a stream of time-interleaved cells.

FIG. 9A illustrates the time interleaving block for a single PLP (S-PLP), and it consists of a convolutional interleaver only.

FIG. 9B illustrates the time interleaving block for a plurality of PLPs (M-PLP), and it can be divided in several sub-blocks as illustrated.

The framing block 14320 maps the interleaved frames onto at least one transmitter frame. The framing block 14320, specifically, receives inputs (e.g. data cell) from at least one physical layer pipes and outputs symbols.

In addition, the framing block 14320 creates at least one special symbol known as preamble symbols. These symbols undergo the same processing in the waveform block mentioned later.

FIG. 10 is a view illustrating an example of a transmission frame according to an exemplary embodiment.

As illustrated in FIG. 10, the transmission frame consists of three parts, the bootstrap, preamble and data payload. Each of the three parts consists of at least one symbol.

Meanwhile, the purpose of the frequency interleaving block 14330 is to ensure that sustained interference in one part of the spectrum will not degrade the performance of a particular PLP disproportionately compared to other PLPs. The frequency interleaver 14330, operating on the all the data cells of one OFDM symbol, maps the data cells from the framining block 14320 onto the N data carriers.

FIG. 11 is a block diagram provided to explain detailed configuration of a Waveform Generation block illustrated in FIG. 1A.

As illustrated in FIG. 11, the Waveform Generation block 14000 includes a pilot inserting block 14100, a MISO block 14200, an IFFT block 14300, a PAPR block 14400, a GI inserting block 14500 and a bootstrap block 14600.

The pilot inserting block 14100 inserts a pilot to various cells within the OFDM frame.

Various cells within the OFDM frame are modulated with reference information whose transmitted value is known to the receiver.

Cells containing the reference information are transmitted at a boosted power level. The cells are called scattered, continual, edge, preamble or frame-closing pilot cells. The value of the pilot information is derived from a reference sequence, which is a series of values, one for each transmitted carrier on any given symbol.

The pilots can be used for frame synchronization, frequency synchronization, time synchronization, channel estimation, transmission mode identification and can also be used to follow the phase noise.

The pilots are modulated according to reference information, and the reference sequence is applied to all the pilots (e.g. scattered, continual edge, preamble and frame closing pilots) in every symbol including preamble and the frame-closing symbol of the frame.

The reference information, taken from the reference sequence, is transmitted in scattered pilot cells in every symbol except the preamble and the frame-closing symbol of the frame.

In addition to the scattered pilots described above, a number of continual pilots are inserted in every symbol of the frame except for Preamble and the frame-closing symbol. The number and location of continual pilots depends on both the FFT size and scattered pilot pattern in use.

The MISO block 14200 applies a MISO processing.

The Transmit Diversity Code Filter Set is a MISO pre-distortion technique that artificially decorrelates signals from multiple transmitters in a Single Frequency Network in order to minimize potential destructive interference. Linear frequency domain filters are used so that the compensation in the receiver can be implemented as part of the equalizer process. The filter design is based on creating all-pass filters with minimized cross-correlation over all filter pairs under the constraints of the number of transmitters Mε{2,3,4} and the time domain span of the filters Nε{64,256}. The longer time domain span filters will increase the decorrelation level, but the effective guard interval length will be decreased by the filter time domain span and this should be taken into consideration when choosing a filter set for a particular network topology.

The IFFT block 14300 specifies the OFDM structure to use for each transmission mode. The transmitted signal is organized in frames. Each frame has a duration of T_(F), and consists of L_(F) OFDM symbols. N frames constitute one super-frame. Each symbol is constituted by a set of K_(total) carriers transmitted with a duration T_(S). Each symbol is composed of a useful part with duration T_(U) and a guard interval with a duration Δ. The guard interval consists of a cyclic continuation of the useful part, T_(U), and is inserted before it.

The PAPR block 14400 applies the Peak to Average Power Reduction technique.

The GI inserting block 14500 inserts the guard interval into each frame.

The bootstrap block 14600 prefixes the bootstrap signal to the front of each frame.

FIG. 12 is a block diagram provided to explain a configuration of signaling information according to an exemplary embodiment.

The input processing block 11000 includes a scheduler 11200. The BICM block 15000 includes an L1 signaling generator 15100, an FEC encoder 15200-1 and 15200-2, a bit interleaver 15300-2, a demux 15400-2, constellation mappers 15500-1 and 15500-2. The L1 signaling generator 15100 may be included in the input processing block 11000, according to an exemplary embodiment.

An n number of service data are mapped to a PLP0 to a PLPn respectively. The scheduler 11200 determines a position, modulation and coding rate for each PLP in order to map a plurality of PLPs to a physical layer of T2. In other words, the scheduler 11200 generates L1 signaling information. The scheduler 11200 may output dynamic field information among L1 post signaling information of a current frame, using the raming/Interleavingblock 13000(FIG. 1) which may be referred to as a frame builder. Further, the scheduler 11200 may transmit the L1 signaling information to the BICM block 15000. The L1 signaling information includes L1 pre signaling information and L1 post signaling information.

The L1 signaling generator 15100 may differentiate the L1 pre signaling information from the L1 post signaling information to output them. The FEC encoders 15200-1 and 15200-2 perform respective encoding operations which include shortening and puncturing for the L1 pre signaling information and the L1 post signaling information. The bit interleaver 15300-2 performs interleaving by bit for the encoded L1 post signaling information. The demux 15400-2 controls robustness of bits by modifying an order of bits constituting cells and outputs the cells which include bits. Two constellation mappers 15500-1 and 15500-2 map the L1 pre signaling information and the L1 post signaling information to constellations, respectively. The L1 pre signaling information and the L1 post signaling information processed through the above described processes are output to be included in each frame by the Framing/Interleaving block 13000(FIG. 1).

FIG. 13 illustrates a structure of an receiving apparatus according to an embodiment of the present invention.

The apparatus 20000 for receiving broadcast signals according to an embodiment of the present invention can correspond to the apparatus 10000 for transmitting broadcast signals, described with reference to FIG. 1. The apparatus 20000 for receiving broadcast signals according to an embodiment of the present invention can include a synchronization & demodulation module 21000, a frame parsing module 22000, a demapping & decoding module 23000, an output processor 24000 and a signaling decoding module 25000. A description will be given of operation of each module of the apparatus 20000 for receiving broadcast signals.

The synchronization & demodulation module 21000 can receive input signals through m Rx antennas, perform signal detection and synchronization with respect to a system corresponding to the apparatus 20000 for receiving broadcast signals and carry out demodulation corresponding to a reverse procedure of the procedure performed by the apparatus 10000 for transmitting broadcast signals.

The frame parsing module 22000 can parse input signal frames and extract data through which a service selected by a user is transmitted. If the apparatus 10000 for transmitting broadcast signals performs interleaving, the frame parsing module 22000 can carry out deinterleaving corresponding to a reverse procedure of interleaving. In this case, the positions of a signal and data that need to be extracted can be obtained by decoding data output from the signaling decoding module 25200 to restore scheduling information generated by the apparatus 10000 for transmitting broadcast signals.

The demapping & decoding module 23000 can convert the input signals into bit domain data and then deinterleave the same as necessary. The demapping & decoding module 23000 can perform demapping for mapping applied for transmission efficiency and correct an error generated on a transmission channel through decoding. In this case, the demapping & decoding module 23000 can obtain transmission parameters necessary for demapping and decoding by decoding the data output from the signaling decoding module 25000.

The output processor 24000 can perform reverse procedures of various compression/signal processing procedures which are applied by the apparatus 10000 for transmitting broadcast signals to improve transmission efficiency. In this case, the output processor 24000 can acquire necessary control information from data output from the signaling decoding module 25000. The output of the output processor 24000 corresponds to a signal input to the apparatus 10000 for transmitting broadcast signals and may be MPEG-TSs, IP streams (v4 or v6) and generic streams.

The signaling decoding module 25000 can obtain PLS information from the signal demodulated by the synchronization & demodulation module 21000. As described above, the frame parsing module 22000, demapping & decoding module 23000 and output processor 24000 can execute functions thereof using the data output from the signaling decoding module 25000.

FIG. 14 illustrates a synchronization & demodulation module according to an embodiment of the present invention.

As shown in FIG. 14, the synchronization & demodulation module 21000 according to an embodiment of the present invention corresponds to a synchronization & demodulation module of an apparatus 20000 for receiving broadcast signals using m Rx antennas and can include m processing blocks for demodulating signals respectively input through m paths. The m processing blocks can perform the same processing procedure. A description will be given of operation of the first processing block 21000 from among the m processing blocks.

The first processing block 21000 can include a tuner 21100, an ADC block 21200, a preamble detector 21300, a guard sequence detector 21400, a waveform transform block 21500, a time/frequency synchronization block 21600, a reference signal detector 21700, a channel equalizer 21800 and an inverse waveform transform block 21900.

The tuner 21100 can select a desired frequency band, compensate for the magnitude of a received signal and output the compensated signal to the ADC block 21200.

The ADC block 21200 can convert the signal output from the tuner 21100 into a digital signal.

The preamble detector 21300 can detect a preamble (or preamble signal or preamble symbol) in order to check whether or not the digital signal is a signal of the system corresponding to the apparatus 20000 for receiving broadcast signals. In this case, the preamble detector 21300 can decode basic transmission parameters received through the preamble.

The guard sequence detector 21400 can detect a guard sequence in the digital signal. The time/frequency synchronization block 21600 can perform time/frequency synchronization using the detected guard sequence and the channel equalizer 21800 can estimate a channel through a received/restored sequence using the detected guard sequence.

The waveform transform block 21500 can perform a reverse operation of inverse waveform transform when the apparatus 10000 for transmitting broadcast signals has performed inverse waveform transform. When the broadcast transmission/reception system according to one embodiment of the present invention is a multi-carrier system, the waveform transform block 21500 can perform FFT. Furthermore, when the broadcast transmission/reception system according to an embodiment of the present invention is a single carrier system, the waveform transform block 21500 may not be used if a received time domain signal is processed in the frequency domain or processed in the time domain.

The time/frequency synchronization block 21600 can receive output data of the preamble detector 21300, guard sequence detector 21400 and reference signal detector 21700 and perform time synchronization and carrier frequency synchronization including guard sequence detection and block window positioning on a detected signal. Here, the time/frequency synchronization block 21600 can feed back the output signal of the waveform transform block 21500 for frequency synchronization.

The reference signal detector 21700 can detect a received reference signal. Accordingly, the apparatus 20000 for receiving broadcast signals according to an embodiment of the present invention can perform synchronization or channel estimation.

The channel equalizer 21800 can estimate a transmission channel from each Tx antenna to each Rx antenna from the guard sequence or reference signal and perform channel equalization for received data using the estimated channel.

The inverse waveform transform block 21900 may restore the original received data domain when the waveform transform block 21500 performs waveform transform for efficient synchronization and channel estimation/equalization. If the broadcast transmission/reception system according to an embodiment of the present invention is a single carrier system, the waveform transform block 21500 can perform FFT in order to carry out synchronization/channel estimation/equalization in the frequency domain and the inverse waveform transform block 21900 can perform IFFT on the channel-equalized signal to restore transmitted data symbols. If the broadcast transmission/reception system according to an embodiment of the present invention is a multi-carrier system, the inverse waveform transform block 21900 may not be used.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.

FIG. 15 illustrates a frame parsing module according to an embodiment of the present invention.

As shown in FIG. 15, the frame parsing module 22000 according to an embodiment of the present invention can include at least one block interleaver 22100 and at least one cell demapper 22200.

The block interleaver 22100 can deinterleave data input through data paths of the m Rx antennas and processed by the synchronization & demodulation module 21000 on a signal block basis. In this case, if the apparatus 10000 for transmitting broadcast signals performs pair-wise interleaving, the block interleaver 22100 can process two consecutive pieces of data as a pair for each input path. Accordingly, the block interleaver 22100 can output two consecutive pieces of data even when deinterleaving has been performed. Furthermore, the block interleaver 22100 can perform a reverse operation of the interleaving operation performed by the apparatus 10000 for transmitting broadcast signals to output data in the original order.

The cell demapper 22200 can extract cells corresponding to common data, cells corresponding to data pipes and cells corresponding to PLS data from received signal frames. The cell demapper 22200 can merge data distributed and transmitted and output the same as a stream as necessary. When two consecutive pieces of cell input data are processed as a pair and mapped in the apparatus 10000 for transmitting broadcast signals, the cell demapper 22200 can perform pair-wise cell demapping for processing two consecutive input cells as one unit as a reverse procedure of the mapping operation of the apparatus 10000 for transmitting broadcast signals.

In addition, the cell demapper 22200 can extract PLS signaling data received through the current frame as PLS-pre & PLS-post data and output the PLS-pre & PLS-post data.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.

FIG. 16 illustrates a demapping & decoding module according to an embodiment of the present invention.

The demapping & decoding module 23000 shown in FIG. 16 can perform a reverse operation of the operation of the bit interleaved and coded & modulation module illustrated in FIG. 1.

The bit interleaved and coded & modulation module of the apparatus 10000 for transmitting broadcast signals according to an embodiment of the present invention can process input data pipes by independently applying SISO, MISO and MIMO thereto for respective paths, as described above. Accordingly, the demapping & decoding module 23000 illustrated in FIG. 16 can include blocks for processing data output from the frame parsing module according to SISO, MISO and MIMO in response to the apparatus 10000 for transmitting broadcast signals.

As shown in FIG. 16, the demapping & decoding module 23000 according to an embodiment of the present invention can include a first block 23100 for SISO, a second block 23200 for MISO, a third block 23300 for MIMO and a fourth block 23400 for processing the PLS-pre/PLS-post information. The demapping & decoding module 23000 shown in FIG. 16 is exemplary and may include only the first block 23100 and the fourth block 23400, only the second block 23200 and the fourth block 23400 or only the third block 23300 and the fourth block 23400 according to design. That is, the demapping & decoding module 23000 can include blocks for processing data pipes equally or differently according to design.

A description will be given of each block of the demapping & decoding module 23000.

The first block 23100 processes an input data pipe according to SISO and can include a time deinterleaver block 23110, a cell deinterleaver block 23120, a constellation demapper block 23130, a cell-to-bit mux block 23140, a bit deinterleaver block 23150 and an FEC decoder block 23160.

The time deinterleaver block 23110 can perform a reverse process of the process performed by the time interleaving block 14310 illustrated in FIG. 8. That is, the time deinterleaver block 23110 can deinterleave input symbols interleaved in the time domain into original positions thereof.

The cell deinterleaver block 23120 can perform a reverse process of the process performed by the cell interleaver block illustrated in FIG. 9a . That is, the cell deinterleaver block 23120 can deinterleave positions of cells spread in one FEC block into original positions thereof. The cell deinterleaver block 23120 may be omitted.

The constellation demapper block 23130 can perform a reverse process of the process performed by the mapper 12300 illustrated in FIG. 5. That is, the constellation demapper block 23130 can demap a symbol domain input signal to bit domain data. In addition, the constellation demapper block 23130 may perform hard decision and output decided bit data. Furthermore, the constellation demapper block 23130 may output a log-likelihood ratio (LLR) of each bit, which corresponds to a soft decision value or probability value. If the apparatus 10000 for transmitting broadcast signals applies a rotated constellation in order to obtain additional diversity gain, the constellation demapper block 23130 can perform 2-dimensional LLR demapping corresponding to the rotated constellation. Here, the constellation demapper block 23130 can calculate the LLR such that a delay applied by the apparatus 10000 for transmitting broadcast signals to the I or Q component can be compensated.

The cell-to-bit mux block 23140 can perform a reverse process of the process performed by the mapper 12300 illustrated in FIG. 5. That is, the cell-to-bit mux block 23140 can restore bit data mapped to the original bit streams.

The bit deinterleaver block 23150 can perform a reverse process of the process performed by the bit interleaver 12200 illustrated in FIG. 5. That is, the bit deinterleaver block 23150 can deinterleave the bit streams output from the cell-to-bit mux block 23140 in the original order.

The FEC decoder block 23460 can perform a reverse process of the process performed by the FEC encoder 12100 illustrated in FIG. 5. That is, the FEC decoder block 23460 can correct an error generated on a transmission channel by performing LDPC decoding and BCH decoding.

The second block 23200 processes an input data pipe according to MISO and can include the time deinterleaver block, cell deinterleaver block, constellation demapper block, cell-to-bit mux block, bit deinterleaver block and FEC decoder block in the same manner as the first block 23100, as shown in FIG. 16. However, the second block 23200 is distinguished from the first block 23100 in that the second block 23200 further includes a MISO decoding block 23210. The second block 23200 performs the same procedure including time deinterleaving operation to outputting operation as the first block 23100 and thus description of the corresponding blocks is omitted.

The MISO decoding block 11110 can perform a reverse operation of the operation of the MISO processing in the apparatus 10000 for transmitting broadcast signals. If the broadcast transmission/reception system according to an embodiment of the present invention uses STBC, the MISO decoding block 11110 can perform Alamouti decoding.

The third block 23300 processes an input data pipe according to MIMO and can include the time deinterleaver block, cell deinterleaver block, constellation demapper block, cell-to-bit mux block, bit deinterleaver block and FEC decoder block in the same manner as the second block 23200, as shown in FIG. 16. However, the third block 23300 is distinguished from the second block 23200 in that the third block 23300 further includes a MIMO decoding block 23310. The basic roles of the time deinterleaver block, cell deinterleaver block, constellation demapper block, cell-to-bit mux block and bit deinterleaver block included in the third block 23300 are identical to those of the corresponding blocks included in the first and second blocks 23100 and 23200 although functions thereof may be different from the first and second blocks 23100 and 23200.

The MIMO decoding block 23310 can receive output data of the cell deinterleaver for input signals of the m Rx antennas and perform MIMO decoding as a reverse operation of the operation of the MIMO processing in the apparatus 10000 for transmitting broadcast signals. The MIMO decoding block 23310 can perform maximum likelihood decoding to obtain optimal decoding performance or carry out sphere decoding with reduced complexity. Otherwise, the MIMO decoding block 23310 can achieve improved decoding performance by performing MMSE detection or carrying out iterative decoding with MMSE detection.

The fourth block 23400 processes the PLS-pre/PLS-post information and can perform SISO or MISO decoding.

The basic roles of the time deinterleaver block, cell deinterleaver block, constellation demapper block, cell-to-bit mux block and bit deinterleaver block included in the fourth block 23400 are identical to those of the corresponding blocks of the first, second and third blocks 23100, 23200 and 23300 although functions thereof may be different from the first, second and third blocks 23100, 23200 and 23300.

The shortened/punctured FEC decoder 23410 can perform de-shortening and de-puncturing on data shortened/punctured according to PLS data length and then carry out FEC decoding thereon. In this case, the FEC decoder used for data pipes can also be used for PLS. Accordingly, additional FEC decoder hardware for the PLS only is not needed and thus system design is simplified and efficient coding is achieved.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.

The demapping & decoding module according to an embodiment of the present invention can output data pipes and PLS information processed for the respective paths to the output processor, as illustrated in FIG. 16.

FIGS. 17 and 18 illustrate output processors according to embodiments of the present invention.

FIG. 17 illustrates an output processor 24000 according to an embodiment of the present invention. The output processor 24000 illustrated in FIG. 17 receives a single data pipe output from the demapping & decoding module and outputs a single output stream.

The output processor 24000 shown in FIG. 17 can include a BB scrambler block 24100, a padding removal block 24200, a CRC-8 decoder block 24300 and a BB frame processor block 24400.

The BB scrambler block 24100 can descramble an input bit stream by generating the same PRBS as that used in the apparatus for transmitting broadcast signals for the input bit stream and carrying out an XOR operation on the PRBS and the bit stream.

The padding removal block 24200 can remove padding bits inserted by the apparatus for transmitting broadcast signals as necessary.

The CRC-8 decoder block 24300 can check a block error by performing CRC decoding on the bit stream received from the padding removal block 24200.

The BB frame processor block 24400 can decode information transmitted through a BB frame header and restore MPEG-TSs, IP streams (v4 or v6) or generic streams using the decoded information.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.

FIG. 18 illustrates an output processor according to another embodiment of the present invention. The output processor 24000 shown in FIG. 18 receives multiple data pipes output from the demapping & decoding module. Decoding multiple data pipes can include a process of merging common data commonly applicable to a plurality of data pipes and data pipes related thereto and decoding the same or a process of simultaneously decoding a plurality of services or service components (including a scalable video service) by the apparatus for receiving broadcast signals.

The output processor 24000 shown in FIG. 18 can include a BB descrambler block, a padding removal block, a CRC-8 decoder block and a BB frame processor block as the output processor illustrated in FIG. 17. The basic roles of these blocks correspond to those of the blocks described with reference to FIG. 17 although operations thereof may differ from those of the blocks illustrated in FIG. 17.

A de-jitter buffer block 24500 included in the output processor shown in FIG. 18 can compensate for a delay, inserted by the apparatus for transmitting broadcast signals for synchronization of multiple data pipes, according to a restored TTO (time to output) parameter.

A null packet insertion block 24600 can restore a null packet removed from a stream with reference to a restored DNP (deleted null packet) and output common data.

A TS clock regeneration block 24700 can restore time synchronization of output packets based on ISCR (input stream time reference) information.

A TS recombining block 24800 can recombine the common data and data pipes related thereto, output from the null packet insertion block 24600, to restore the original MPEG-TSs, IP streams (v4 or v6) or generic streams. The TTO, DNT and ISCR information can be obtained through the BB frame header.

An in-band signaling decoding block 24900 can decode and output in-band physical layer signaling information transmitted through a padding bit field in each FEC frame of a data pipe.

The output processor shown in FIG. 18 can BB-descramble the PLS-pre information and PLS-post information respectively input through a PLS-pre path and a PLS-post path and decode the descrambled data to restore the original PLS data. The restored PLS data is delivered to a system controller included in the apparatus for receiving broadcast signals. The system controller can provide parameters necessary for the synchronization & demodulation module, frame parsing module, demapping & decoding module and output processor module of the apparatus for receiving broadcast signals.

The above-described blocks may be omitted or replaced by blocks having similar r identical functions according to design.

FIG. 19 is a block diagram to illustrate a configuration of a transmitting apparatus according to an exemplary embodiment. Referring to FIG. 19, the transmitting apparatus 100 includes an encoder 110, an interleaver 120, and a modulator 130 (or a constellation mapper).

The encoder 110 generates a low density parity check (LDPC) codeword by performing LDPC encoding based on a parity check matrix. To achieve this, the encoder 110 may include an LDPC encoder (not shown) to perform the LDPC encoding.

Specifically, the encoder 110 LDPC-encodes information word (or information) bits to generate the LDPC codeword which is formed of information word bits and parity bits (that is, LDPC parity bits). Here, bits input to the encoder 110 may be used as the information word bits. Also, since an LDPC code is a systematic code, the information word bits may be included in the LDPC codeword as they are.

The LDPC codeword is formed of the information word bits and the parity bits. For example, the LDPC codeword is formed of N_(ldpc) number of bits, and includes K_(ldpc) number of information word bits and N_(parity)=N_(ldpc)−K_(ldpc) number of parity bits.

In this case, the encoder 110 may generate the LDPC codeword by performing the LDPC encoding based on the parity check matrix. That is, since the LDPC encoding is a process for generating an LDPC codeword to satisfy H·C^(T)=0, the encoder 110 may use the parity check matrix when performing the LDPC encoding. Herein, H is a parity check matrix and C is an LDPC codeword.

For the LDPC encoding, the transmitting apparatus 100 may include a memory and may pre-store parity check matrices of various formats.

For example, the transmitting apparatus 100 may pre-store parity check matrices which are defined in Digital Video Broadcasting-Cable version 2 (DVB-C2), Digital Video Broadcasting-Satellite-Second Generation (DVB-S2), Digital Video Broadcasting-Second Generation Terrestrial (DVB-T2), etc., or may pre-store parity check matrices which are defined in the North America digital broadcasting standard system Advanced Television System Committee (ATSC) 3.0 standards, which are currently being established. However, this is merely an example and the transmitting apparatus 100 may pre-store parity check matrices of other formats in addition to these parity check matrices.

Hereinafter, a parity check matrix according to various exemplary embodiments will be explained in detail with reference to the drawings. In the parity check matrix, elements other than elements having 1 have 0.

For example, the parity check matrix according to an exemplary embodiment may have a configuration of FIG. 20.

Referring to FIG. 20, a parity check matrix 200 is formed of an information word submatrix (or an information submatrix) 210 corresponding to information word bits, and a parity submatrix 220 corresponding to parity bits.

The information word submatrix 210 includes K_(ldpc) number of columns and the parity submatrix 220 includes N_(parity)=N_(ldpc)−K_(ldpc) number of columns. The number of rows of the parity check matrix 200 is identical to the number of columns of the parity submatrix 220, N_(parity)=N_(ldpc)−K_(ldpc).

In addition, in the parity check matrix 200, N_(ldpc) is a length of an LDPC codeword, K_(ldpc) is a length of information word bits, and N_(parity)=N_(ldpc)−K_(ldpc) is a length of parity bits. The length of the LDPC codeword, the information word bits, and the parity bits mean the number of bits included in each of the LDPC codeword, the information word bits, and the parity bits.

Hereinafter, the configuration of the information word submatrix 210 and the parity submatrix 220 will be explained in detail.

The information word submatrix 210 includes K_(ldpc) number of columns (that is, 0^(th) column to (K_(ldpc)−1)^(th) column), and follows the following rules:

First, M number of columns from among K_(ldpc) number of columns of the information word submatrix 210 belong to the same group, and K_(ldpc) number of columns is divided into K_(ldpc)/M number of column groups. In each column group, a column is cyclic-shifted from an immediately previous column by Q_(ldpc). That is, Q_(ldpc) may be a cyclic shift parameter value regarding columns in a column group of the information word submatrix 210 of the parity check matrix 200.

Herein, M is an interval at which a pattern of a column group, which includes a plurality of columns, is repeated in the information word submatrix 210 (e.g., M=360), and Q_(ldpc) is a size by which one column is cyclic-shifted from an immediately previous column in a same column group in the information word submatrix 210. Also, M is a common divisor of N_(ldpc) and K_(ldpc) and is determined to satisfy Q_(ldpc)=(N_(ldpc)−K_(ldpc))/M. Here, M and Q_(ldpc) are integers and K_(ldpc)/M is also an integer. M and Q_(ldpc) may have various values according to a length of the LDPC codeword and a code rate (CR)(or, coding rate).

For example, when M=360 and the length of the LDPC codeword, N_(ldpc), is 64800, Q_(ldpc) may be defined as in table 1 presented below, and, when M=360 and the length N_(ldpc) of the LDPC codeword is 16200, Q_(ldpc) may be defined as in table 2 presented below.

TABLE 1 Code Rate N_(ldpc) M Q_(ldpc)  5/15 64800 360 120  6/15 64800 360 108  7/15 64800 360  96  8/15 64800 360  84  9/15 64800 360  72 10/15 64800 360  60 11/15 64800 360  48 12/15 64800 360  36 13/15 64800 360  24

TABLE 2 Code Rate N_(ldpc) M Q_(ldpc)  5/15 16200 360 30  6/15 16200 360 27  7/15 16200 360 24  8/15 16200 360 21  9/15 16200 360 18 10/15 16200 360 15 11/15 16200 360 12 12/15 16200 360  9 13/15 16200 360  6

Second, when the degree of the 0^(th) column of the i^(th) column group (i=0, 1, . . . , K_(ldpc)/M−1) is D_(i) (herein, the degree is the number of value 1 existing in each column and all columns belonging to the same column group have the same degree), and a position (or an index) of each row where 1 exists in the 0^(th) column of the i^(th) column group is R_(i,0) ⁽⁰⁾, R_(i,0) ⁽¹⁾, . . . , R_(i,0) ^((D) ^(i) ⁻¹⁾, an index R_(i,j) ^((k)) of a row where k^(th) 1 is located in the j^(th) column in the i^(th) column group is determined by following Equation 1:

R _(i,j) ^((k)) =R _(i,(j−1)) ^((k)) +Q _(ldpc) mod(N _(ldpc) −K _(ldpc))  (1)

where k=0, 1, 2, . . . D_(i)−1; i=0, 1, . . . , K_(ldpc)/M−1; and j=1, 2, . . . , M−1.

Equation 1 can be expressed as following Equation 2:

R _(i,j) ^((k)) ={R _(i,0) ^((k))+(j mod M)×Q _(ldpc)} mod(N _(ldpc) −K _(ldpc))  (2),

where k=0, 1, 2, . . . D_(i)−1; i=0, 1, . . . , K_(ldpc)/M−1; and j=1, 2, . . . , M−1. Since j=1, 2, . . . , M−1, (j mod M) of Equation 2 may be regarded as j.

In the above equations, R_(i,j) ^((k)) is an index of a row where k^(th) is located in the j^(th) column in the i^(th) column group, N_(ldpc) is a length of an LDPC codeword, K_(ldpc) is a length of information word bits, D_(i) is a degree of columns belonging to the i^(th) column group, M is the number of columns belonging to a single column group, and Q_(ldpc) is a size by which each column in the column group is cyclic-shifted.

As a result, referring to these equations, when only R_(i,0) ^((k)) is known, the index R_(i,j) ^((k)) of the row where the k^(th) 1 is located in the j^(th) column in the i^(th) column group can be known. Therefore, when the index value of the row where the k^(th) 1 is located in the 0^(th) column of each column group is stored, a position of column and row where 1 is located in the parity check matrix 200 having the configuration of FIG. 20 (that is, in the information word submatrix 210 of the parity check matrix 200) can be known.

According to the above-described rules, all of the columns belonging to the i^(th) column group have the same degree D_(i). Accordingly, the LDPC codeword which stores information on the parity check matrix according to the above-described rules may be briefly expressed as follows.

For example, when N_(ldpc) is 30, K_(ldpc) is 15, and Q_(ldpc) is 3, position information of the row where 1 is located in the 0^(th) column of the three column groups may be expressed by a sequence of Equations 3 and may be referred to as “weight-1 position sequence”.

R _(1,0) ⁽¹⁾=1,R _(1,0) ⁽²⁾=2,R _(1,0) ⁽³⁾=8,R _(1,0) ⁽⁴⁾=10,

R _(2,0) ⁽¹⁾=0,R _(2,0) ⁽²⁾=9,R _(2,0) ⁽³⁾=13,

R _(3,0) ⁽¹⁾=0,R _(3,0) ⁽²⁾=14.  (3)

where R_(i,j) ^((k)) is an index of a row where k^(th) 1 is located in the j^(th) column in the i^(th) column group.

The weight-1 position sequence like Equation 3 which expresses an index of a row where 1 is located in the 0^(th) column of each column group may be briefly expressed as in Table 3 presented below:

TABLE 3 1 2 8 10 0 9 13 0 14

Table 3 shows positions of elements having value 1 in the parity check matrix, and the i^(th) weight-1 position sequence is expressed by indexes of rows where 1 is located in the 0^(th) column belonging to the i^(th) column group.

The information word submatrix 210 of the parity check matrix according to an exemplary embodiment may be defined as in Tables 4 to 8 presented below, based on the above descriptions.

Specifically, Tables 4 to 8 show indexes of rows where 1 is located in the 0^(th) column of the i^(th) column group of the information word submatrix 210. That is, the information word submatrix 210 is formed of a plurality of column groups each including M number of columns, and positions of 1 in the 0^(th) column of each of the plurality of column groups may be defined by Tables 4 to 8.

Herein, the indexes of the rows where 1 is located in the 0^(th) column of the i^(th) column group mean “addresses of parity bit accumulators”. The “addresses of parity bit accumulators” have the same meaning as defined in the DVB-C2/S2/T2 standards or the ATSC 3.0 standards which are currently being established, and thus, a detailed explanation thereof is omitted.

For example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate is 6/15, and M is 360, the indexes of the rows where 1 is located in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are as shown in Table 4 presented below:

TABLE 4 Index of row where 1 is located in the 0th column of the ith column group 0 1606 3402 4961 6751 7132 11516 12300 12482 12592 13342 13764 14123 21576 23946 24533 25376 25667 26836 31799 34173 35462 36153 36740 37085 37152 37468 37658 1 4621 5007 6910 8732 9757 11508 13099 15513 16335 18052 19512 21319 23663 25628 27208 31333 32219 33003 33239 33447 36200 36473 36938 37201 37283 37495 38642 2 16 1094 2020 3080 4194 5098 5631 6877 7889 8237 9804 10067 11017 11366 13136 13354 15379 18934 20199 24522 26172 28666 30386 32714 36390 37015 37162 3 700 897 1708 6017 6490 7372 7825 9546 10398 16605 18561 18745 21625 22137 23693 24340 24966 25015 26995 28586 28895 29687 33938 34520 34858 37056 38297 4 159 2010 2573 3617 4452 4958 5556 5832 6481 8227 9924 10836 14954 15594 16623 18065 19249 22394 22677 23408 23731 24076 24776 27007 28222 30343 38371 5 3118 3545 4768 4992 5227 6732 8170 9397 10522 11508 15536 20218 21921 28599 29445 29758 29968 31014 32027 33685 34378 35867 36323 36728 36870 38335 38623 6 1264 4254 6936 9165 9486 9950 10861 11653 13697 13961 15164 15665 18444 19470 20313 21189 24371 26431 26999 28086 28251 29261 31981 34015 35850 36129 37186 7 111 1307 1628 2041 2524 5358 7988 8191 10322 11905 12919 14127 15515 15711 17061 19024 21195 22902 23727 24401 24608 25111 25228 27338 35398 37794 38196 8 961 3035 7174 7948 13355 13607 14971 18189 18339 18665 18875 19142 20615 21136 21309 21758 23366 24745 25849 25982 27583 30006 31118 32106 36469 36583 37920 9 2990 3549 4273 4808 5707 6021 6509 7456 8240 10044 12262 12660 13085 14750 15680 16049 21587 23997 25803 28343 28693 34393 34860 35490 36021 37737 38296 10 955 4323 5145 6885 8123 9730 11840 12216 19194 20313 23056 24248 24830 25268 26617 26801 28557 29753 30745 31450 31973 32839 33025 33296 35710 37366 37509 11 264 605 4181 4483 5156 7238 8863 10939 11251 12964 16254 17511 20017 22395 22818 23261 23422 24064 26329 27723 28186 30434 31956 33971 34372 36764 38123 12 520 2562 2794 3528 3860 4402 5676 6963 8655 9018 9783 11933 16336 17193 17320 19035 20606 23579 23769 24123 24966 27866 32457 34011 34499 36620 37526 13 10106 10637 10906 34242 14 1856 15100 19378 21848 15 943 11191 27806 29411 16 4575 6359 13629 19383 17 4476 4953 18782 24313 18 5441 6381 21840 35943 19 9638 9763 12546 30120 20 9587 10626 11047 25700 21 4088 15298 28768 35047 22 2332 6363 8782 28863 23 4625 4933 28298 30289 24 3541 4918 18257 31746 25 1221 25233 26757 34892 26 8150 16677 27934 30021 27 8500 25016 33043 38070 28 7374 10207 16189 35811 29 611 18480 20064 38261 30 25416 27352 36089 38469 31 1667 17614 25839 32776 32 4118 12481 21912 37945 33 5573 13222 23619 31271 34 18271 26251 27182 30587 35 14690 26430 26799 34355 36 13688 16040 20716 34558 37 2740 14957 23436 32540 38 3491 14365 14681 36858 39 4796 6238 25203 27854 40 1731 12816 17344 26025 41 19182 21662 23742 27872 42 6502 13641 17509 34713 43 12246 12372 16746 27452 44 1589 21528 30621 34003 45 12328 20515 30651 31432 46 3415 22656 23427 36395 47 632 5209 25958 31085 48 619 3690 19648 37778 49 9528 13581 26965 36447 50 2147 26249 26968 28776 51 15698 18209 30683 52 1132 19888 34111 53 4608 25513 38874 54 475 1729 34100 55 7348 32277 38587 56 182 16473 33082 57 3865 9678 21265 58 4447 20151 27618 59 6335 14371 38711 60 704 9695 28858 61 4856 9757 30546 62 1993 19361 30732 63 756 28000 29138 64 3821 24076 31813 65 4611 12326 32291 66 7628 21515 34995 67 1246 13294 30068 68 6466 33233 35865 69 14484 23274 38150 70 21269 36411 37450 71 23129 26195 37653

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate is 8/15, and M is 360, the indexes of the rows where 1 is located in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are as shown in Table 5 presented below:

TABLE 5 i Index of row where 1 is located in the 0th column of the ith column group 0 2768 3039 4059 5856 6245 7013 8157 9341 9802 10470 11521 12083 16610 18361 20321 24601 27420 28206 29788 1 2739 8244 8891 9157 12624 12973 15534 16622 16919 18402 18780 19854 20220 20543 22306 25540 27478 27678 28053 2 1727 2268 6246 7815 9010 9556 10134 10472 11389 14599 15719 16204 17342 17666 18850 22058 25579 25860 29207 3 28 1346 3721 5565 7019 9240 12355 13109 14800 16040 16839 17369 17631 19357 19473 19891 20381 23911 29683 4 869 2450 4386 5316 6160 7107 10362 11132 11271 13149 16397 16532 17113 19894 22043 22784 27383 28615 28804 5 508 4292 5831 8559 10044 10412 11283 14810 15888 17243 17538 19903 20528 22090 22652 27235 27384 28208 28485 6 389 2248 5840 6043 7000 9054 11075 11760 12217 12565 13587 15403 19422 19528 21493 25142 27777 28566 28702 7 1015 2002 5764 6777 9346 9629 11039 11153 12690 13068 13990 16841 17702 20021 24106 26300 29332 30081 30196 8 1480 3084 3467 4401 4798 5187 7851 11368 12323 14325 14546 16360 17158 18010 21333 25612 26556 26906 27005 9 6925 8876 12392 14529 15253 15437 19226 19950 20321 23021 23651 24393 24653 26668 27205 28269 28529 29041 29292 10 2547 3404 3538 4666 5126 5468 7695 8799 14732 15072 15881 17410 18971 19609 19717 22150 24941 27908 29018 11 888 1581 2311 5511 7218 9107 10454 12252 13662 15714 15894 17025 18671 24304 25316 25556 28489 28977 29212 12 1047 1494 1718 4645 5030 6811 7868 8146 10611 15767 17682 18391 22614 23021 23763 25478 26491 29088 29757 13 59 1781 1900 3814 4121 8044 8906 9175 11156 14841 15789 16033 16755 17292 18550 19310 22505 29567 29850 14 1952 3057 4399 9476 10171 10769 11335 11569 15002 19501 20621 22642 23452 24360 25109 25290 25828 28505 29122 15 2895 3070 3437 4764 4905 6670 9244 11845 13352 13573 13975 14600 15871 17996 19672 20079 20579 25327 27958 16 612 1528 2004 4244 4599 4926 5843 7684 10122 10443 12267 14368 18413 19058 22985 24257 26202 26596 27899 17 1361 2195 4146 6708 7158 7538 9138 9998 14862 15359 16076 18925 21401 21573 22503 24146 24247 27778 29312 18 5229 6235 7134 7655 9139 13527 15408 16058 16705 18320 19909 20901 22238 22437 23654 25131 27550 28247 29903 19 697 2035 4887 5275 6909 9166 11805 15338 16381 18403 20425 20688 21547 24590 25171 26726 28848 29224 29412 20 5379 17329 22659 23062 21 11814 14759 22329 22936 22 2423 2811 10296 12727 23 8460 15260 16769 17290 24 14191 14608 29536 30187 25 7103 10069 20111 22850 26 4285 15413 26448 29069 27 548 2137 9189 10928 28 4581 7077 23382 23949 29 3942 17248 19486 27922 30 8668 10230 16922 26678 31 6158 9980 13788 28198 32 12422 16076 24206 29887 33 8778 10649 18747 22111 34 21029 22677 27150 28980 35 7918 15423 27672 27803 36 5927 18086 23525 37 3397 15058 30224 38 24016 25880 26268 39 1096 4775 7912 40 3259 17301 20802 41 129 8396 15132 42 17825 28119 28676 43 2343 8382 28840 44 3907 18374 20939 45 1132 1290 8786 46 1481 4710 28846 47 2185 3705 26834 48 5496 15681 21854 49 12697 13407 22178 50 12788 21227 22894 51 629 2854 6232 52 2289 18227 27458 53 7593 21935 23001 54 3836 7081 12282 55 7925 18440 23135 56 497 6342 9717 57 11199 22046 30067 58 12572 28045 28990 59 1240 2023 10933 60 19566 20629 25186 61 6442 13303 28813 62 4765 10572 16180 63 552 19301 24286 64 6782 18480 21383 65 11267 12288 15758 66 771 5652 15531 67 16131 20047 25649 68 13227 23035 24450 69 4839 13467 27488 70 2852 4677 22993 71 2504 28116 29524 72 12518 17374 24267 73 1222 11859 27922 74 9660 17286 18261 75 232 11296 29978 76 9750 11165 16295 77 4894 9505 23622 78 10861 11980 14110 79 2128 15883 22836 80 6274 17243 21989 81 10866 13202 22517 82 11159 16111 21608 83 3719 18787 22100 84 1756 2020 23901 85 20913 29473 30103 86 2729 15091 26976 87 4410 8217 12963 88 5395 24564 28235 89 3859 17909 23051 90 5733 26005 29797 91 1935 3492 29773 92 11903 21380 29914 93 6091 10469 29997 94 2895 8930 15594 95 1827 10028 20070

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate is 10/15, and M is 360, the indexes of rows where 1 exists in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are defined as shown in Table 6 below.

TABLE 6 i Index of row where 1 is located in the 0th column of the ith column group 0 979 1423 4166 4609 6341 8258 10334 10548 14098 14514 17051 17333 17653 17830 17990 1 2559 4025 6344 6510 9167 9728 11312 14856 17104 17721 18600 18791 19079 19697 19840 2 3243 6894 7950 10539 12042 13233 13938 14752 16449 16727 17025 18297 18796 19400 21577 3 3272 3574 6341 6722 9191 10807 10957 12531 14036 15580 16651 17007 17309 19415 19845 4 155 4598 10201 10975 11086 11296 12713 15364 15978 16395 17542 18164 18451 18612 20617 5 1128 1999 3926 4069 5558 6085 6337 8386 10693 12450 15438 16223 16370 17308 18634 6 2408 2929 3630 4357 5852 7329 8536 8695 10603 11003 14304 14937 15767 18402 21502 7 199 3066 6446 6849 8973 9536 10452 12857 13675 15913 16717 17654 19802 20115 21579 8 312 870 2095 2586 5517 6196 6757 7311 7368 13046 15384 18576 20349 21424 21587 9 985 1591 3248 3509 3706 3847 6174 6276 7864 9033 13618 15675 16446 18355 18843 10 975 3774 4083 5825 6166 7218 7633 9657 10103 13052 14240 17320 18126 19544 20208 11 1795 2005 2544 3418 6148 8051 9066 9725 10676 10752 11512 15171 17523 20481 21059 12 167 315 1824 2325 2640 2868 6070 6597 7016 8109 9815 11608 16142 17912 19625 13 1298 1896 3039 4303 4690 8787 12241 13600 14478 15492 16602 17115 17913 19466 20597 14 568 3695 6045 6624 8131 8404 8590 9059 9246 11570 14336 18657 18941 19218 21506 15 228 1889 1967 2299 3011 5074 7044 7596 7689 9534 10244 10697 11691 17902 21410 16 1330 1579 1739 2234 3701 3865 5713 6677 7263 11172 12143 12765 17121 20011 21436 17 303 1668 2501 4925 5778 5985 9635 10140 10820 11779 11849 12058 15650 20426 20527 18 698 2484 3071 3219 4054 4125 5663 5939 6928 7086 8054 12173 16280 17945 19302 19 232 1619 3040 4901 7438 8135 9117 9233 10131 13321 17347 17436 18193 18586 19929 20 12 3721 6254 6609 7880 8139 10437 12262 13928 14065 14149 15032 15694 16264 18883 21 482 915 1548 1637 6687 9338 10163 11768 11970 15524 15695 17386 18787 19210 19340 22 1291 2500 4109 4511 5099 5194 10014 13165 13256 13972 15409 16113 16214 18584 20998 23 1761 4778 7444 7740 8129 8341 8931 9136 9207 10003 10678 13959 17673 18194 20990 24 3060 3522 5361 5692 6833 8342 8792 11023 11211 11548 11914 13987 15442 15541 19707 25 1322 2348 2970 5632 6349 7577 8782 9113 9267 9376 12042 12943 16680 16970 21321 26 6785 11960 21455 27 1223 15672 19550 28 5976 11335 20385 29 2818 9387 15317 30 2763 3554 18102 31 5230 11489 18997 32 5809 15779 20674 33 2620 17838 18533 34 3025 9342 9931 35 3728 5337 12142 36 2520 6666 9164 37 12892 15307 20912 38 10736 12393 16539 39 1075 2407 12853 40 4921 5411 18206 41 5955 15647 16838 42 6384 10336 19266 43 429 10421 17266 44 4880 10431 12208 45 2910 11895 12442 46 7366 18362 18772 47 4341 7903 14994 48 4564 6714 7378 49 4639 8652 18871 50 15787 18048 20246 51 3241 11079 13640 52 1559 2936 15881 53 2737 6349 10881 54 10394 16107 17073 55 8207 9043 12874 56 7805 16058 17905 57 11189 15767 17764 58 5823 12923 14316 59 11080 20390 20924 60 568 8263 17411 61 1845 3557 6562 62 2890 10936 14756 63 9031 14220 21517 64 3529 12955 15902 65 413 6750 8735 66 6784 12092 16421 67 12019 13794 15308 68 12588 15378 17676 69 8067 14589 19304 70 1244 5877 6085 71 15897 19349 19993 72 1426 2394 12264 73 3456 8931 12075 74 13342 15273 20351 75 9138 13352 20798 76 7031 7626 14081 77 4280 4507 15617 78 4170 10569 14335 79 3839 7514 16578 80 4688 12815 18782 81 4861 7858 9435 82 605 5445 12912 83 2280 4734 7311 84 6668 8128 12638 85 3733 10621 19534 86 13933 18316 19341 87 1786 3037 21566 88 2202 13239 16432 89 4882 5808 9300 90 4580 8484 16754 91 14630 17502 18269 92 6889 11119 12447 93 8162 9078 16330 94 6538 17851 18100 95 17763 19793 20816 96 2183 11907 17567 97 6640 14428 15175 98 877 12035 14081 99 1336 6468 12328 100 5948 9146 12003 101 3782 5699 12445 102 1770 7946 8244 103 7384 12639 14989 104 1469 11586 20959 105 7943 10450 15907 106 5005 8153 10035 107 17750 18826 21513 108 4725 8041 10112 109 3837 16266 17376 110 11340 17361 17512 111 1269 4611 4774 112 2322 10813 16157 113 16752 16843 18959 114 70 4325 18753 115 3165 8153 15384 116 160 8045 16823 117 14112 16724 16792 118 4291 7667 18176 119 5943 19879 20721

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate is 10/15, and M is 360, the indexes of rows where 1 exists in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are defined as shown in Table 7 below.

TABLE 7 i Index of row where 1 is located in the 0th column of the ith column group 0 316 1271 3692 9495 12147 12849 14928 16671 16938 17864 19108 20502 21097 21115 1 2341 2559 2643 2816 2865 5137 5331 7000 7523 8023 10439 10797 13208 15041 2 5556 6858 7677 10162 10207 11349 12321 12398 14787 15743 15859 15952 19313 20879 3 349 573 910 2702 3654 6214 9246 9353 10638 11772 14447 14953 16620 19888 4 204 1390 2887 3835 6230 6533 7443 7876 9299 10291 10896 13960 18287 20086 5 541 2429 2838 7144 8523 8637 10490 10585 11074 12074 15762 16812 17900 18548 6 733 1659 3838 5323 5805 7882 9429 10682 13697 16909 18846 19587 19592 20904 7 1134 2136 4631 4653 4718 5197 10410 11666 14996 15305 16048 17417 18960 20303 8 734 1001 1283 4959 10016 10176 10973 11578 12051 15550 15915 19022 19430 20121 9 745 4057 5855 9885 10594 10989 13156 13219 13351 13631 13685 14577 17713 20386 10 968 1446 2130 2502 3092 3787 5323 8104 8418 9998 11681 13972 17747 17929 11 3020 3857 5275 5786 6319 8608 11943 14062 17144 17752 18001 18453 19311 21414 12 709 747 1038 2181 5320 8292 10584 10859 13964 15009 15277 16953 20675 21509 13 1663 3247 5003 5760 7186 7360 10346 14211 14717 14792 15155 16128 17355 17970 14 516 578 1914 6147 9419 11148 11434 13289 13325 13332 19106 19257 20962 21556 15 5009 5632 6531 9430 9886 10621 11765 13969 16178 16413 18110 18249 20616 20759 16 457 2686 3318 4608 5620 5858 6480 7430 9602 12691 14664 18777 20152 20848 17 33 2877 5334 6851 7907 8654 10688 15401 16123 17942 17969 18747 18931 20224 18 87 897 7636 8663 11425 12288 12672 14199 16435 17615 17950 18953 19667 20281 19 1042 1832 2545 2719 2947 3672 3700 6249 6398 6833 11114 14283 17694 20477 20 326 488 2662 2880 3009 5357 6587 8882 11604 14374 18781 19051 19057 20508 21 854 1294 2436 2852 4903 6466 7761 9072 9564 10321 13638 15658 16946 19119 22 194 899 1711 2408 2786 5391 7108 8079 8716 11453 17303 19484 20989 21389 23 1631 3121 3994 5005 7810 8850 10315 10589 13407 17162 18624 18758 19311 20301 24 736 2424 4792 5600 6370 10061 16053 16775 18600 25 1254 8163 8876 9157 12141 14587 16545 17175 18191 26 388 6641 8974 10607 10716 14477 16825 17191 18400 27 5578 6082 6824 7360 7745 8655 11402 11665 12428 28 3603 8729 13463 14698 15210 19112 19550 20727 21052 29 48 1732 3805 5158 15442 16909 19854 21071 21579 30 11707 14014 21531 31 1542 4133 4925 32 10083 13505 21198 33 14300 15765 16752 34 778 1237 11215 35 1325 3199 14534 36 2007 14510 20599 37 1996 5881 16429 38 5111 15018 15980 39 4989 10681 12810 40 3763 10715 16515 41 2259 10080 15642 42 9032 11319 21305 43 3915 15213 20884 44 11150 15022 20201 45 1147 6749 19625 46 12139 12939 18870 47 3840 4634 10244 48 1018 10231 17720 49 2708 13056 13393 50 5781 11588 18888 51 1345 2036 5252 52 5908 8143 15141 53 1804 13693 18640 54 10433 13965 16950 55 9568 10122 15945 56 547 6722 14015 57 321 12844 14095 58 2632 10513 14936 59 6369 11995 20321 60 9920 19136 21529 61 1990 2726 10183 62 5763 12118 15467 63 503 10006 19564 64 9839 11942 19472 65 11205 13552 15389 66 8841 13797 19697 67 124 6053 18224 68 6477 14406 21146 69 1224 8027 16011 70 3046 4422 17717 71 739 12308 17760 72 4014 4130 7835 73 2266 5652 11981 74 2711 7970 18317 75 2196 15229 17217 76 8636 13302 16764 77 5612 15010 16657 78 615 1249 4639 79 3821 12073 18506 80 1066 16522 21536 81 11307 18363 19740 82 3240 8560 10391 83 3124 11424 20779 84 1604 8861 17394 85 2083 7400 8093 86 3218 7454 9155 87 9855 15998 20533 88 316 2850 20652 89 5583 9768 10333 90 7147 7713 18339 91 12607 17428 21418 92 14216 16954 18164 93 8477 15970 18488 94 1632 8032 9751 95 4573 9080 13507 96 11747 12441 13876 97 1183 15605 16675 98 4408 10264 17109 99 5495 7882 12150 100 1010 3763 5065 101 9828 18054 21599 102 6342 7353 15358 103 6362 9462 19999 104 7184 13693 17622 105 4343 4654 10995 106 7099 8466 18520 107 11505 14395 15138 108 6779 16691 18726 109 7146 12644 20196 110 5865 16728 19634 111 4657 8714 21246 112 4580 5279 18750 113 3767 6620 18905 114 9209 13093 17575 115 12486 15875 19791 116 8046 14636 17491 117 2120 4643 13206 118 6186 9675 12601 119 784 5770 21585

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate is 12/15, and M is 360, the indexes of rows where 1 exists in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are defined as shown in Table 8 below.

TABLE 8 i Index of row where 1 is located in the 0th column of the ith column group 0 584 1472 1621 1867 3338 3568 3723 4185 5126 5889 7737 8632 8940 9725 1 221 445 590 3779 3835 6939 7743 8280 8448 8491 9367 10042 11242 12917 2 4662 4837 4900 5029 6449 6687 6751 8684 9936 11681 11811 11886 12089 12909 3 2418 3018 3647 4210 4473 7447 7502 9490 10067 11092 11139 11256 12201 12383 4 2591 2947 3349 3406 4417 4519 5176 6672 8498 8863 9201 11294 11376 12184 5 27 101 197 290 871 1727 3911 5411 6676 8701 9350 10310 10798 12439 6 1765 1897 2923 3584 3901 4048 6963 7054 7132 9165 10184 10824 11278 12669 7 2183 3740 4808 5217 5660 6375 6787 8219 8466 9037 10353 10583 11118 12762 8 73 1594 2146 2715 3501 3572 3639 3725 6959 7187 8406 10120 10507 10691 9 240 732 1215 2185 2788 2830 3499 3881 4197 4991 6425 7061 9756 10491 10 831 1568 1828 3424 4319 4516 4639 6018 9702 10203 10417 11240 11518 12458 11 2024 2970 3048 3638 3676 4152 5284 5779 5926 9426 9945 10873 11787 11837 12 1049 1218 1651 2328 3493 4363 5750 6483 7613 8782 9738 9803 11744 11937 13 1193 2060 2289 2964 3478 4592 4756 6709 7162 8231 8326 11140 11908 12243 14 978 2120 2439 3338 3850 4589 6567 8745 9656 9708 10161 10542 10711 12639 15 2403 2938 3117 3247 3711 5593 5844 5932 7801 10152 10226 11498 12162 12941 16 1781 2229 2276 2533 3582 3951 5279 5774 7930 9824 10920 11038 12340 12440 17 289 384 1980 2230 3464 3873 5958 8656 8942 9006 10175 11425 11745 12530 18 155 354 1090 1330 2002 2236 3559 3705 4922 5958 6576 8564 9972 12760 19 303 876 2059 2142 5244 5330 6644 7576 8614 9598 10410 10718 11033 12957 20 3449 3617 4408 4602 4727 6182 8835 8928 9372 9644 10237 10747 11655 12747 21 811 2565 2820 8677 8974 9632 11069 11548 11839 12107 12411 12695 12812 12890 22 972 4123 4943 6385 6449 7339 7477 8379 9177 9359 10074 11709 12552 12831 23 842 973 1541 2262 2905 5276 6758 7099 7894 8128 8325 8663 8875 10050 24 474 791 968 3902 4924 4965 5085 5908 6109 6329 7931 9038 9401 10568 25 1397 4461 4658 5911 6037 7127 7318 8678 8924 9000 9473 9602 10446 12692 26 1334 7571 12881 27 1393 1447 7972 28 633 1257 10597 29 4843 5102 11056 30 3294 8015 10513 31 1108 10374 10546 32 5353 7824 10111 33 3398 7674 8569 34 7719 9478 10503 35 2997 9418 9581 36 5777 6519 11229 37 1966 5214 9899 38 6 4088 5827 39 836 9248 9612 40 483 7229 7548 41 7865 8289 9804 42 2915 11098 11900 43 6180 7096 9481 44 1431 6786 8924 45 748 6757 8625 46 3312 4475 7204 47 1852 8958 11020 48 1915 2903 4006 49 6776 10886 12531 50 2594 9998 12742 51 159 2002 12079 52 853 3281 3762 53 5201 5798 6413 54 3882 6062 12047 55 4133 6775 9657 56 228 6874 11183 57 7433 10728 10864 58 7735 8073 12734 59 2844 4621 11779 60 3909 7103 12804 61 6002 9704 11060 62 5864 6856 7681 63 3652 5869 7605 64 2546 2657 4461 65 2423 4203 9111 66 244 1855 4691 67 1106 2178 6371 68 391 1617 10126 69 250 9259 10603 70 3435 4614 6924 71 1742 8045 9529 72 7667 8875 11451 73 4023 6108 6911 74 8621 10184 11650 75 6726 10861 12348 76 3228 6302 7388 77 1 1137 5358 78 381 2424 8537 79 3256 7508 10044 80 1980 2219 4569 81 2468 5699 10319 82 2803 3314 12808 83 8578 9642 11533 84 829 4585 7923 85 59 329 5575 86 1067 5709 6867 87 1175 4744 12219 88 109 2518 6756 89 2105 10626 11153 90 5192 10696 10749 91 6260 7641 8233 92 2998 3094 11214 93 3398 6466 11494 94 6574 10448 12160 95 2734 10755 12780 96 1028 7958 10825 97 8545 8602 10793 98 392 3398 11417 99 6639 9291 12571 100 1067 7919 8934 101 1064 2848 12753 102 6076 8656 12690 103 5504 6193 10171 104 1951 7156 7356 105 4389 4780 7889 106 526 4804 9141 107 1238 3648 10464 108 2587 5624 12557 109 5560 5903 11963 110 1134 2570 3297 111 10041 11583 12157 112 1263 9585 12912 113 3744 7898 10646 114 45 9074 10315 115 1051 6188 10038 116 2242 8394 12712 117 3598 9025 12651 118 2295 3540 5610 119 1914 4378 12423 120 1766 3635 12759 121 5177 9586 11143 122 943 3590 11649 123 4864 6905 10454 124 5852 6042 10421 125 6095 8285 12349 126 2070 7171 8563 127 718 12234 12716 128 512 10667 11353 129 3629 6485 7040 130 2880 8865 11466 131 4490 10220 11796 132 5440 8819 9103 133 5262 7543 12411 134 516 7779 10940 135 2515 5843 9202 136 4684 5994 10586 137 573 2270 3324 138 7870 8317 10322 139 6856 7638 12909 140 1583 7669 10781 141 8141 9085 12555 142 3903 5485 9992 143 4467 11998 12904

In the above-described examples, the length of the LDPC codeword is 64800 and the code rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and the position of 1 in the information word submatrix 210 may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.

According to an exemplary embodiment, even when the order of numbers in a sequence corresponding to the i^(th) column group of the parity check matrix 200 as shown in the above-described Tables 4 to 8 is changed, the changed parity check matrix is a parity check matrix used for the same code. Therefore, a case in which the order of numbers in the sequence corresponding to the i^(th) column group in Tables 4 to 8 is changed is covered by the inventive concept.

According to an exemplary embodiment, even when the arrangement order of sequences corresponding to each column group is changed in Tables 4 to 8, cycle characteristics on a graph of a code and algebraic characteristics such as degree distribution are not changed. Therefore, a case in which the arrangement order of the sequences shown in Tables 4 to 8 is changed is also covered by the inventive concept.

In addition, even when a multiple of Q_(ldpc) is equally added to all sequences corresponding to a certain column group in Tables 4 to 8, the cycle characteristics on the graph of the code or the algebraic characteristics such as degree distribution are not changed. Therefore, a result of equally adding a multiple of Q_(ldpc) to the sequences shown in Tables 4 to 8 is also covered by the inventive concept. However, it should be noted that, when the resulting value obtained by adding the multiple of Q_(ldpc) to a given sequence is greater than or equal to (N_(ldpc)−K_(ldpc)), a value obtained by applying a modulo operation for (N_(ldpc)−K_(ldpc)) to the resulting value should be applied instead.

Once positions of the rows where 1 exists in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are defined as shown in Tables 4 to 8, positions of rows where 1 exists in another column of each column group may be defined since the positions of the rows where 1 exists in the 0^(th) column are cyclic-shifted by Q_(ldpc) in the next column.

For example, in the case of Table 4, in the 0^(th) column of the 0^(th) column group of the information word submatrix 210, 1 exists in the 1606^(th) row, 3402^(nd) row, 4961^(st) row, . . . .

In this case, since Q_(ldpc)=(N_(ldpc)−K_(ldpc))/M=(64800-25920)/360=108, the indexes of the rows where 1 is located in the 1^(st) column of the 0^(th) column group may be 1714(=1606+108), 3510(=3402+108), 5069(=4961+108), . . . , and the indexes of the rows where 1 is located in the 2^(nd) column of the 0^(th) column group may be 1822(=1714+108), 3618(=3510+108), 5177(=5069+108), . . . .

In the above-described method, the indexes of the rows where 1 is located in all rows of each column group may be defined.

The parity submatrix 220 of the parity check matrix 200 shown in FIG. 20 may be defined as follows:

The parity submatrix 220 includes N_(ldpc)−K_(ldpc) number of columns (that is, K_(ldpc) ^(th) column to (N_(lpdc)−1)^(th) column), and has a dual diagonal or staircase configuration. Accordingly, the degree of columns except the last column (that is, (N_(ldpc)−1)^(th) column) from among the columns included in the parity submatrix 220 is 2, and the degree of the last column is 1.

As a result, the information word submatrix 210 of the parity check matrix 200 may be defined by Tables 4 to 8, and the parity submatrix 220 of the parity check matrix 200 may have a dual diagonal configuration.

When the columns and rows of the parity check matrix 200 shown in FIG. 20 are permutated based on Equation 4 and Equation 5, the parity check matrix shown in FIG. 20 may be changed to a parity check matrix 300 shown in FIG. 21.

Q _(ldpc) ·i+j

M·j+i(0≦i<M,0≦j<Q _(ldpc))  (4)

K _(ldpc) +Q _(ldpc) ·k+l

K _(ldpc) +M·l+k(0≦k<M,0≦l<Q _(ldpc)  (5)

The method for permutating based on Equation 4 and Equation 5 will be explained below. Since row permutation and column permutation apply the same principle, the row permutation will be explained by the way of an example.

In the case of the row permutation, regarding the X^(th) row, i and j satisfying X=Q_(ldpc)×i+j are calculated and the X^(th) row is permutated by assigning the calculated i and j to M×j+i. For example, regarding the 7^(th) row, i and j satisfying 7=2×i+j are 3 and 1, respectively. Therefore, the 7^(th) row is permutated to the 13^(th) row (10×1+3=13).

When the row permutation and the column permutation are performed in the above-described method, the parity check matrix of FIG. 20 may be converted into the parity check matrix of FIG. 21.

Referring to FIG. 21, the parity check matrix 300 is divided into a plurality of partial blocks, and a quasi-cyclic matrix of M×M corresponds to each partial block.

Accordingly, the parity check matrix 300 having the configuration of FIG. 21 is formed of matrix units of M×M. That is, the submatrices of M×M are arranged in the plurality of partial blocks, constituting the parity check matrix 300.

Since the parity check matrix 300 is formed of the quasi-cyclic matrices of M×M, M number of columns may be referred to as a column block and M number of rows may be referred to as a row block. Accordingly, the parity check matrix 300 having the configuration of FIG. 21 is formed of N_(qc) _(_) _(column)=N_(ldpc)/M number of column blocks and N_(qc) _(_) _(row)=N_(parity)/M number of row blocks.

Hereinafter, the submatrix of M×M will be explained.

First, the (N_(qc) _(_) _(column)−1)^(th) column block of the 0^(th) row block has a form shown in Equation 6 presented below:

$\begin{matrix} {A = \begin{bmatrix} 0 & 0 & \ldots & 0 & 0 \\ 1 & 0 & \ldots & 0 & 0 \\ 0 & 1 & \ldots & 0 & 0 \\ \vdots & \vdots & \vdots & \vdots & \vdots \\ 0 & 0 & \ldots & 1 & 0 \end{bmatrix}} & (6) \end{matrix}$

As described above, A 330 is an M×M matrix, values of the 0^(th) row and the (M−1)^(th) column are all “0”, and, regarding 0≦i≦(M−2), the (i+1)^(th) row of the i^(th) column is “1” and the other values are “0”.

Second, regarding 0≦i≦(N_(ldpc)−K_(ldpc))/M−1 in the parity submatrix 320, the i^(th) row block of the (K_(ldpc)/M+i)^(th) column block is configured by a unit matrix I_(M×M) 340. In addition, regarding 0≦i≦(N_(ldpc)−K_(ldpc))/M−2, the (i+1)^(th) row block of the (K_(ldpc)/M+i)^(th) column block is configured by a unit matrix I_(M×M) 340.

Third, a block 350 constituting the information word submatrix 310 may have a cyclic-shifted format of a cyclic matrix P, P^(a) ^(ij) , or an added format of the cyclic-shifted matrix P^(a) ^(ij) of the cyclic matrix P (or an overlapping format).

For example, a format in which the cyclic matrix P is cyclic-shifted to the right by 1 may be expressed by Equation 7 presented below:

$\begin{matrix} {P = \begin{bmatrix} 0 & 1 & 0 & \; & 0 \\ 0 & 0 & 1 & \ldots & 0 \\ \vdots & \vdots & \vdots & \; & \vdots \\ 0 & 0 & 0 & \ldots & 1 \\ 1 & 0 & 0 & \; & 0 \end{bmatrix}} & (7) \end{matrix}$

The cyclic matrix P is a square matrix having an M×M size and is a matrix in which a weight of each of M number of rows is 1 and a weight of each of M number of columns is 1. When a_(ij) is 0, the cyclic matrix P, that is, P⁰ indicates a unit matrix I_(M×M), and when a_(ij) is ∞, P^(∞) is a zero matrix.

A submatrix existing where the i^(th) row block and the j^(th) column block intersect in the parity check matrix 300 of FIG. 21 may be P^(a) ^(ij) . Accordingly, i and j indicate the number of row blocks and the number of column blocks in the partial blocks corresponding to the information word. Accordingly, in the parity check matrix 300, the total number of columns is N_(ldpc)=M×N_(qc) _(_) _(column), and the total number of rows is N_(parity)=M×N_(qc) _(_) _(row). That is, the parity check matrix 300 is formed of N_(qc) _(_) _(column) number of “column blocks” and N_(qc) _(_) _(row) number of “row blocks”.

Hereinafter, a method for performing LDPC encoding based on the parity check matrix 200 as shown in FIG. 20 will be explained. An LDPC encoding process when the parity check matrix 200 is defined as shown in Table 4 by way of an example will be explained for the convenience of explanation.

First, when information word bits having a length of K_(ldpc) are [i₀, i₁, i₂, . . . , i_(K) _(ldpc) ⁻¹], and parity bits having a length of N_(ldpc)−K_(ldpc) are [p₀, p₁, p₂, . . . p_(N) _(lpdc) _(−K) _(ldpc) ⁻¹], the LDPC encoding is performed by the following process.

Step 1) Parity bits are initialized as ‘0’. That is, p₀=p₁=p₂= . . . =p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹=0.

Step 2) The 0^(th) information word bit i₀ is accumulated in a parity bit having the address of the parity bit defined in the first row (that is, the row of i=0) of table 4 as the index of the parity bit. This may be expressed by Equation 8 presented below:

P ₁₆₀₆ =P ₁₆₀₆ ⊕i ₀ P ₂₄₅₃₃ =P ₂₄₅₃₃ ⊕i ₀

P ₃₄₀₂ =P ₃₄₀₂ ⊕i ₀ P ₂₅₃₇₆ =P ₂₅₃₇₆ ⊕i ₀

P ₄₉₆₁ =P ₄₉₆₁ ⊕i ₀ P ₂₅₆₆₇ =P ₂₅₆₆₇ ⊕i ₀

P ₆₇₅₁ =P ₆₇₅₁ ⊕i ₀ P ₂₆₈₃₆ =P ₂₆₈₃₆ ⊕i ₀

P ₇₁₃₂ =P ₇₁₃₂ ⊕i ₀ P ₃₁₇₉₉ =P ₃₁₇₉₉ ⊕i ₀

P ₁₁₅₁₆ =P ₁₁₅₁₆ ⊕i ₀ P ₃₄₁₇₃ =P ₃₄₁₇₃ ⊕i ₀

P ₁₂₃₀₀ =P ₁₂₃₀₀ ⊕i ₀ P ₃₅₄₆₂ =P ₃₅₄₆₂ ⊕i ₀

P ₁₂₄₈₂ =P ₁₂₄₈₂ ⊕i ₀ P ₃₆₁₅₃ =P ₃₆₁₅₃ ⊕i ₀

P ₁₂₅₉₂ =P ₁₂₅₉₂ ⊕i ₀ P ₃₆₇₄₀ =P ₃₆₇₄₀ ⊕i ₀

P ₁₃₃₄₂ =P ₁₃₃₄₂ ⊕i ₀ P ₃₇₀₈₅ =P ₃₇₀₈₅ ⊕i ₀

P ₁₃₇₆₄ =P ₁₃₇₆₄ ⊕i ₀ P ₃₇₁₅₂ =P ₃₇₁₅₂ ⊕i ₀

P ₁₄₁₂₃ =P ₁₄₁₂₃ ⊕i ₀ P ₃₇₄₆₈ =P ₃₇₄₆₈ ⊕i ₀

P ₂₁₅₇₆ =P ₂₁₅₇₆ ⊕i ₀ P ₃₇₆₅₈ =P ₃₇₆₅₈ ⊕i ₀

P ₂₃₉₄₆ =P ₂₃₉₄₆ ⊕i ₀  (8)

Herein, i₀ is a 0^(th) information word bit, p_(i) is an ith parity bit, and ⊕ is a binary operation. According to the binary operation, 1⊕1 equals 0, 1⊕0 equals 1, 0⊕1 equals 1, 0⊕0 equals 0.

Step 3) The other 359 information word bits i_(m) (m=1, 2, . . . , 359) are accumulated in the parity bit. The other information word bits may belong to the same column group as that of i₀. In this case, the address of the parity bit may be determined based on Equation 9 presented below:

(x+(m mod 360)×Q _(ldpc))mod(N _(ldpc) −K _(ldpc))  (9)

Herein, x is an address of a parity bit accumulator corresponding to the information word bit i₀, and Q_(ldpc) is a size by which each column is cyclic-shifted in the information word submatrix, and may be 108 in the case of table 4. In addition, since m=1, 2, . . . , 359, (m mod 360) in Equation 9 may be regarded as m.

As a result, information word bits i_(m) (m=1, 2, . . . , 359) are accumulated in the parity bits having the address of the parity bit calculated based on Equation 9 as the index. For example, an operation as shown in Equation 10 presented below may be performed for the information word bit i₁:

P ₁₇₁₄ =P ₁₇₁₄ ⊕i ₁ P ₂₄₆₄₁ =P ₂₄₆₄₁ ⊕i ₁

P ₃₅₁₀ =P ₃₅₁₀ ⊕i ₁ P ₂₅₄₈₄ =P ₂₅₄₈₄ ⊕i ₁

P ₅₀₆₉ =P ₅₀₆₉ ⊕i ₁ P ₂₅₇₇₅ =P ₂₅₇₇₅ ⊕i ₁

P ₆₈₅₉ =P ₆₈₅₉ ⊕i ₁ P ₂₆₉₄₄ =P ₂₆₉₄₄ ⊕i ₁

P ₇₂₄₀ =P ₇₂₄₀ ⊕i ₁ P ₃₁₉₀₇ =P ₃₁₉₀₇ ⊕i ₁

P ₁₁₆₂₄ =P ₁₁₆₂₄ ⊕i ₁ P ₃₄₂₈₁ =P ₃₄₂₈₁ ⊕i ₁

P ₁₂₄₀₈ =P ₁₂₄₀₈₁ ⊕i ₁ P ₃₅₅₇₀ =P ₃₅₅₇₀ ⊕i ₁

P ₁₂₅₉₀ =P ₁₂₅₉₀ ⊕i ₁ P ₃₆₂₆₁ =P ₃₆₂₆₁ ⊕i ₁

P ₁₂₇₀₀ =P ₁₂₇₀₀ ⊕i ₁ P ₃₆₈₄₈ =P ₃₆₈₄₈ ⊕i ₁

P ₁₃₄₅₀ =P ₁₃₄₅₀ ⊕i ₁ P ₃₇₁₉₃ =P ₃₇₁₉₃ ⊕i ₁

P ₁₃₈₇₂ =P ₁₃₈₇₂ ⊕i ₁ P ₃₇₂₆₀ =P ₃₇₂₆₀ ⊕i ₁

P ₁₄₂₃₁ =P ₁₄₂₃₁ ⊕i ₁ P ₃₇₅₇₆ =P ₃₇₅₇₆ ⊕i ₁

P ₂₁₆₈₄ =P ₂₁₆₈₄ ⊕i ₁ P ₃₇₇₆₆ =P ₃₇₇₆₆ ⊕i ₁

P ₂₄₀₅₄ =P ₂₄₀₅₄ ⊕i ₁  (10)

Herein, i₁ is a 1^(st) information word bit, p_(i) is an ith parity bit, and ⊕ is a binary operation. According to the binary operation, 1⊕1 equals 0, 1⊕0 equals 1, 0⊕1 equals 1, 0⊕0 equals 0.

Step 4) The 360^(th) information word bits i₃₆₀ is accumulated in a parity bit having the address of the parity bit defined in the 2^(nd) row (that is, the row of i=1) of table 4 as the index of the parity bit.

Step 5) The other 359 information word bits belonging to the same group as that of the information word bit i₃₆₀ are accumulated in the parity bit. In this case, the address of the parity bit may be determined based on Equation 9. However, in this case, x is the address of the parity bit accumulator corresponding to the information word bit i₃₆₀.

Step 6) Steps 4 and 5 described above are repeated for all of the column groups of table 4.

Step 7) As a result, a parity bit p_(i) is calculated based on Equation 11 presented below. In this case, i is initialized as 1.

p _(i) =p _(i) ⊕p _(i−1) i=1,2, . . . ,N _(ldpc) −K _(ldpc)−1  (11)

In Equation 11, p_(i) is an ith parity bit, N_(ldpc) is a length of an LDPC codeword, K_(lpdc) is a length of an information word of the LDPC codeword, and ⊕ is a binary operation.

As a result, the encoder 110 may calculate the parity bits according to the above-described method.

In another example, a parity check matrix according to an exemplary embodiment may have a configuration as shown in FIG. 22.

Referring to FIG. 22, the parity check matrix 400 may be formed of 5 matrices A, B, C, Z, and D. Hereinafter, the configuration of each matrix will be explained to explain the configuration of the parity check matrix 400.

First, M₁, M₂, Q₁, and Q₂, which are parameter values related to the parity check matrix 400 as shown in FIG. 22, may be defined as shown in table 9 presented below according to the length and the code rate of the LDPC codeword.

TABLE 9 Sizes Rate Length M₁ M₂ Q₁ Q₂ 1/15 16200 2520 12600 7 35 64800 1080 59400 3 165 2/15 16200 3240 10800 9 30 64800 1800 54360 5 151 3/15 16200 1080 11880 3 33 64800 1800 50040 5 139 4/15 16200 1080 10800 3 30 64800 1800 45720 5 127 5/15 16200 720 10080 2 28 64800 1440 41760 4 116 6/15 16200 1080 8640 3 24 64800 1080 37800 3 105

The matrix A is formed of K number of columns and g number of rows, and the matrix C is formed of K+g number of columns and N−K−g number of rows. Herein, K is a length of information word bits, and N is a length of the LDPC codeword.

Indexes of rows where 1 is located in the 0^(th) column of the ith column group in the matrix A and the matrix C may be defined based on table 10 according to the length and the code rate of the LDPC codeword. In this case, an interval at which a pattern of a column is repeated in each of the matrix A and the matrix C, that is, the number of columns belonging to the same group, may be 360.

For example, when the length N of the LDPC codeword is 64800 and the code rate is 6/15, the indexes of rows where 1 is located in the 0^(th) column of the ith column group in the matrix A and the matrix C are defined as shown in table 10 presented below:

TABLE 10 Index of row i where 1 is located in the 0th column of the ith column group 0 71 276 856 6867 12964 17373 18159 26420 28460 28477 1 257 322 672 2533 5316 6578 9037 10231 13845 36497 2 233 765 904 1366 3875 13145 15409 18620 23910 30825 3 100 224 405 12776 13868 14787 16781 23886 29099 31419 4 23 496 891 2512 12589 14074 19392 20339 27658 28684 5 473 712 759 1283 4374 9898 12551 13814 24242 32728 6 511 567 815 11823 17106 17900 19338 22315 24396 26448 7 45 733 836 1923 3727 17468 25746 33806 35995 36657 8 17 487 675 2670 3922 5145 18009 23993 31073 36624 9 72 751 773 1937 17324 28512 30666 30934 31016 31849 10 257 343 594 14041 19141 24914 26864 28809 32055 34753 11 99 241 491 2650 9670 17433 17785 18988 22235 30742 12 198 299 655 6737 8304 10917 16092 19387 20755 37690 13 351 916 926 18151 21708 23216 30321 33578 34052 37949 14 54 332 373 2010 3332 5623 16301 34337 36451 37861 15 139 257 1068 11090 20289 29694 29732 32640 35133 36404 16 457 885 968 2115 4956 5422 5949 17570 26673 32387 17 137 570 619 5006 6099 7979 14429 16650 25443 32789 18 46 282 287 10258 18383 20258 27186 27494 28429 38266 19 445 486 1058 1868 9976 11294 20364 23695 30826 35330 20 134 900 931 12518 14544 17715 19623 21111 33868 34570 21 62 66 586 8020 20270 23831 31041 31965 32224 35189 22 174 290 784 6740 14673 17642 26286 27382 33447 34879 23 332 675 1033 1838 12004 15439 20765 31721 34225 38863 24 527 558 832 3867 6318 8317 10883 13466 18427 25377 25 431 780 1021 1112 2873 7675 13059 17793 20570 20771 26 339 536 1015 5725 6916 10846 14487 21156 28123 32614 27 456 830 1078 7511 11801 12362 12705 17401 28867 34032 28 222 538 989 5593 6022 8302 14008 23445 25127 29022 29 37 393 788 3025 7768 11367 22276 22761 28232 30394 30 234 257 1045 1307 2908 6337 26530 28142 34129 35997 31 35 46 978 9912 9978 12567 17843 24194 34887 35206 32 39 959 967 5027 10847 14657 18859 28075 28214 36325 33 275 477 823 11376 18073 28997 30521 31661 31941 32116 34 185 580 966 11733 12013 12760 13358 19372 32534 35504 35 760 891 1046 11150 20358 21638 29930 31014 33050 34840 36 360 389 1057 5316 5938 14186 16404 32445 34021 35722 37 306 344 679 5224 6674 10305 18753 25583 30585 36943 38 103 171 1016 8780 11741 12144 19470 20955 22495 27377 39 818 832 894 3883 14279 14497 22505 28129 28719 31246 40 215 411 760 5886 25612 28556 32213 32704 35901 36130 41 229 489 1067 2385 8587 20565 23431 28102 30147 32859 42 288 664 980 8138 8531 21676 23787 26708 28798 34490 43 89 552 847 6656 9889 23949 26226 27080 31236 35823 44 66 142 443 3339 3813 7977 14944 15464 19186 25983 45 605 876 931 16682 17669 25800 28220 33432 35738 37382 46 346 423 806 5669 7668 8789 9928 19724 24039 27893 47 48 460 1055 3512 7389 7549 20216 22180 28221 35437 48 187 636 824 1678 4508 13588 19683 21750 30311 33480 49 25 768 935 2856 8187 9052 21850 29941 33217 34293 50 349 624 716 2698 6395 6435 8974 10649 15932 17378 51 336 410 871 3582 9830 10885 13892 18027 19203 36659 52 176 849 1078 17302 19379 27964 28164 28720 32557 35495 53 234 890 1075 9431 9605 9700 10113 11332 12679 24268 54 516 638 733 8851 19871 22740 25791 30152 32659 35568 55 253 830 879 2086 16885 22952 23765 25389 34656 37293 56 94 954 998 2003 3369 6870 7321 29856 31373 34888 57 79 350 933 4853 6252 11932 12058 21631 24552 24876 58 246 647 778 4036 10391 10656 13194 32335 32360 34179 59 149 339 436 6971 8356 8715 11577 22376 28684 31249 60 36 149 220 6936 18408 19192 19288 23063 28411 35312 61 273 683 1042 6327 10011 18041 21704 29097 30791 31425 62 46 138 722 2701 10984 13002 19930 26625 28458 28965 63 12 1009 1040 1990 2930 5302 21215 22625 23011 29288 64 125 241 819 2245 3199 8415 21133 26786 27226 38838 65 45 476 1075 7393 15141 20414 31244 33336 35004 38391 66 432 578 667 1343 10466 11314 11507 23314 27720 34465 67 248 291 556 1971 3989 8992 18000 19998 23932 34652 68 68 694 837 2246 7472 7873 11078 12868 20937 35591 69 272 924 949 2030 4360 6203 9737 19705 19902 38039 70 21 314 979 2311 2632 4109 19527 21920 31413 34277 71 197 253 804 1249 4315 10021 14358 20559 27099 30525 72 9802 16164 17499 22378 22403 22704 26742 29908 73 9064 10904 12305 14057 16156 26000 32613 34536 74 5178 6319 10239 19343 25628 30577 31110 32291

In the above-described example, the length of the LDPC codeword is 64800 and the code rate 6/15. However, this is merely an example and the indexes of rows where 1 is located in the 0^(th) column of the ith column group in the matrix A and the matrix C may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.

Hereinafter, positions of rows where 1 exists in the matrix A and the matrix C will be explained with reference to table 10 by way of an example.

Since the length N of the LDPC codeword is 64800 and the code rate is 6/15 in table 10, M₁=1080, M₂=37800, Q₁=3, and Q₂=105 in the parity check matrix 400 defined by table 10 with reference to table 9.

Herein, Q₁ is a size by which columns of the same column group are cyclic-shifted in the matrix A, and Q₂ is a size by which columns of the same column group are cyclic-shifted in the matrix C.

In addition, Q₁=M₁/L, Q₂=M₂/L, M₁=g, and M₂=N−K−g, and L is an interval at which a pattern of a column is repeated in the matrix A and the matrix C, and for example, may be 360.

The index of the row where 1 is located in the matrix A and the matrix C may be determined based on the M₁ value.

For example, since M₁=1080 in the case of table 10, the positions of the rows where 1 exists in the 0^(th) column of the ith column group in the matrix A may be determined based on values smaller than 1080 from among the index values of table 10, and the positions of the rows where 1 exists in the 0^(th) column of the ith column group in the matrix C may be determined based on values greater than or equal to 1080 from among the index values of table 10.

Specifically, in table 10, the sequence corresponding to the 0^(th) column group is “71, 276, 856, 6867, 12964, 17373, 18159, 26420, 28460, 28477”. Accordingly, in the case of the 0^(th) column of the 0^(th) column group of the matrix A, 1 may be located in the 71^(st) row, 276^(th) row, and 856^(th) row, and, in the case of the 0^(th) column of the 0^(th) column group of the matrix C, 1 may be located in the 6867^(th) row, 12964^(th) row, 17373^(rd) row, 18159^(th) row, 26420^(th) row, 28460^(th) row, and 28477^(th) row.

Once positions of 1 in the 0^(th) column of each column group of the matrix A are defined, positions of rows where 1 exists in another column of each column group may be defined by cyclic-shifting from the previous column by Q₁. Once positions of 1 in the 0^(th) column of each column group of the matrix C are defined, position of rows where 1 exists in another column of each column group may be defined by cyclic-shifting from the previous column by Q₂.

In the above-described example, in the case of the 0^(th) column of the 0^(th) column group of the matrix A, 1 exists in the 71^(st) row, 276^(th) row, and 856^(th) row. In this case, since Q₁=3, the indexes of rows where 1 exists in the 1^(st) column of the 0^(th) column group are 74(=71+3), 279(=276+3), and 859(=856+3), and the index of rows where 1 exists in the 2^(nd) column of the 0^(th) column group are 77(=74+3), 282 (=279+3), and 862(=859+3).

In the case of the 0^(th) column of the 0^(th) column group of the matrix C, 1 exists in the 6867^(th) row, 12964^(th) row, 17373^(rd) row, 18159^(th) row, 26420^(th) row, 28460^(th) row, and 28477^(th) row. In this case, since Q₂=105, the index of rows where 1 exists in the 1^(st) column of the 0^(th) column group are 6972(=6867+105), 13069(=12964+105), 17478(=17373+105), 18264(=18159+105), 26525(=26420+105), 28565(=28460+105), 28582(=28477+105), and the indexes of rows where 1 exists in the 2^(nd) column of the 0^(th) column group are 7077(=6972+105), 13174(=13069+105), 17583(=17478+105), 18369(=18264+105), 26630(=26525+105), 28670(=28565+105), 28687(=28582+105).

In this method, the positions of rows where 1 exists in all column groups of the matrix A and the matrix C are defined.

The matrix B may have a dual diagonal configuration, the matrix D may have a diagonal configuration (that is, the matrix D is an identity matrix), and the matrix Z may be a zero matrix.

As a result, the parity check matrix 400 shown in FIG. 22 may be defined by the matrices A, B, C, D, and Z having the above-described configurations.

Hereinafter, a method for performing LDPC encoding based on the parity check matrix 400 shown in FIG. 22 will be explained. An LDPC encoding process when the parity check matrix 400 is defined as shown in Table 10 by way of an example will be explained for the convenience of explanation.

For example, when an information word block S=(s₀, s₁, S_(K−1)) is LDPC-encoded, an LDPC codeword Λ=(λ₀, λ₁, . . . , λ_(N−1))=(s₀, s₁, . . . , S_(K−1), p₀, p₁, . . . , P_(M) ₁ _(+M) ₂ ⁻¹) including a parity bit P=(p₀, p₁, . . . , P_(M) ₁ _(+M) ₂ ⁻¹) may be generated.

M₁ and M₂ indicate the size of the matrix B having the dual diagonal configuration and the size of the matrix C having the diagonal configuration, respectively, and M₁=g, M₂=N−K−g.

A process of calculating a parity bit is as follows. In the following explanation, the parity check matrix 400 is defined as shown in table 10 by way of an example, for the convenience of explanation.

Step 1) λ and p are initialized as λ_(i)=s_(i) (i=0, 1, . . . , K−1), p_(j)=0 (j=0, 1, . . . , M₁+M₂−1).

Step 2) The 0^(th) information word bit λ₀ is accumulated in the address of the parity bit defined in the first row (that is, the row of i=0) of table 10. This may be expressed by Equation 12 presented below:

P ₇₁ =P ₇₁⊕λ₀ P ₁₇₃₇₃ =P ₁₇₃₇₃⊕λ₀

P ₂₇₆ =P ₂₇₆⊕λ₀ P ₁₈₁₅₉ =P ₁₈₁₅₉⊕λ₀

P ₈₅₆ =P ₈₅₆⊕λ₀ P ₂₆₄₂₀ =P ₂₆₄₂₀⊕λ₀

P ₆₈₆₇ =P ₆₈₆₇⊕λ₀ P ₂₈₄₆₀ =P ₂₈₄₆₀⊕λ₀

P ₁₂₉₆₄ =P ₁₂₉₆₄⊕λ₀ P ₂₈₄₇₇ =P ₂₈₄₇₇⊕λ₀  (12)

Step 3) Regarding the next L−1 number of information word bits λ_(m) (m=1, 2, . . . , L−1), λ_(m) is accumulated in the parity bit address calculated based on Equation 13 presented below:

(χ+m×Q ₁)mod M ₁(if χ<M ₁)

M ₁+{(χ−M ₁ +m×Q ₂)mod M ₂}(if χ≧M ₁)  (13)

Herein, x is an address of a parity bit accumulator corresponding to the 0^(th) information word bit λ₀.

In addition, Q₁=M₁/L and Q₂=M₂/L. In addition, since the length N of the LDPC codeword is 64800 and the code rate is 6/15 in table 10, M₁=1080, M₂=37800, Q₁=3, Q₂=105, and L=360 with reference to table 9.

Accordingly, an operation as shown in Equation 14 presented below may be performed for the 1^(st) information word bit λ₁:

P ₇₄ =P ₇₄⊕λ₁ P ₁₇₄₇₈ =P ₁₇₄₇₈⊕λ₁

P ₂₇₉ =P ₂₇₉⊕λ₁ P ₁₈₂₆₄ =P ₁₈₂₆₄⊕λ₁

P ₈₅₉ =P ₈₅₉⊕λ₁ P ₂₆₅₂₅ =P ₂₆₅₂₅⊕λ₁

P ₆₉₇₂ =P ₆₉₇₂⊕λ₁ P ₂₈₅₆₅ =P ₂₈₅₆₅⊕λ₁

P ₁₃₀₆₉ =P ₁₃₀₆₉⊕λ₁ P ₂₈₅₈₂ =P ₂₈₅₈₂⊕λ₁  (14)

Step 4) Since the same address of the parity bit as in the second row (that is the row of i=1) of table 10 is given to the Lth information word bit λ_(L), in a similar method to the above-described method, the address of the parity bit regarding the next L−1 number of information word bits λ_(m) (m=L+1, L+2, . . . 2L−1) is calculated based on Equation 13. In this case, x is the address of the parity bit accumulator corresponding to the information word bit λ_(L), and may be obtained based on the second row of table 10.

Step 5) The above-described processes are repeated for L number of new information word bits of each group by considering new rows of table 10 as the address of the parity bit accumulator.

Step 6) After the above-described processes are repeated for the codeword bits λ₀ to λ_(K−1), values regarding Equation 15 presented below are calculated in sequence from i=1:

P _(i) =P _(i) ⊕P _(i−1)(i=1,2, . . . ,M ₁−1)  (15)

Step 7) Parity bits 4 to λ_(K+M) ₁ ⁻¹ corresponding to the matrix B having the dual diagonal configuration are calculated based on Equation 16 presented below:

λ_(K+L×t+s) =p _(Q) ₁ _(×S+t)(0≦s<L,0≦t<Q ₁)  (16)

Step 8) The address of the parity bit accumulator regarding L number of new codeword bits λ_(K) to λ_(K+M) ₁ ⁻¹ of each group is calculated based on table 10 and Equation 13.

Step 9) After the codeword bits λ_(K) to λ_(K+M) ₁ ⁻¹ are calculated, parity bits λ_(K+M) ₁ to λ_(K+M) ₁ _(+M) ₂ ⁻¹ corresponding to the matrix C having the diagonal configuration are calculated based on Equation 17 presented below:

λ_(K+M) ₁ _(+L×t+s) =p _(M) ₁ _(+Q) ₂ _(×S+t)(0≦s<L,0≦t<Q ₂)  (17)

As a result, the parity bits may be calculated in the above-described method.

Referring back to FIG. 19, the encoder 110 may perform the LDPC encoding by using various code rates such as 3/15, 4/15, 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15, etc. In addition, the encoder 110 may generate an LDPC codeword having various lengths such as 16200, 64800, etc., based on the length of the information word bits and the code rate.

In this case, the encoder 110 may perform the LDPC encoding by using the parity check matrix, and the parity check matrix is configured as shown in FIGS. 20 to 22.

In addition, the encoder 110 may perform Bose, Chaudhuri, Hocquenghem (BCH) encoding as well as LDPC encoding. To achieve this, the encoder 110 may further include a BCH encoder (not shown) to perform BCH encoding.

In this case, the encoder 110 may perform encoding in an order of BCH encoding and LDPC encoding. Specifically, the encoder 110 may add BCH parity bits to input bits by performing BCH encoding and LDPC-encodes the information word bits including the input bits and the BCH parity bits, thereby generating the LDPC codeword.

The interleaver 120 interleaves the LDPC codeword. That is, the interleaver 120 receives the LDPC codeword from the encoder 110, and interleaves the LDPC codeword based on various interleaving rules.

In particular, the interleaver 120 may interleave the LDPC codeword such that a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword (that is, a plurality of groups or a plurality of blocks) is mapped onto a predetermined bit of a modulation symbol. Accordingly, the modulator 130 may map a bit included in a predetermined group from among the plurality of groups of the LDPC codeword onto a predetermined bit of the modulation symbol.

To achieve this, as shown in FIG. 23, the interleaver 120 may include a parity interleaver 121, a group interleaver (or a group-wise interleaver 122), a group twist interleaver 123 and a block interleaver 124.

The parity interleaver 121 interleaves the parity bits constituting the LDPC codeword.

Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the configuration of FIG. 20, the parity interleaver 121 may interleave only the parity bits of the LDPC codeword by using Equations 18 presented below:

u _(i) =c _(i) for 0≦i<K _(ldpc), and

u _(K) _(ldpc) _(+M·t+s) =c _(K) _(ldpc) _(+Q) _(ldpc) _(·s+t) for 0≦s<M,0≦t<Q _(ldpc)  (18),

where M is an interval at which a pattern of a column group is repeated in the information word submatrix 210, that is, the number of columns included in a column group (for example, M=360), and Q_(ldpc) is a size by which each column is cyclic-shifted in the information word submatrix 210. That is, the parity interleaver 121 performs parity interleaving with respect to the LDPC codeword c=(c₀, c₁, . . . , c_(N) _(ldpc) ⁻¹), and outputs U=(u₀, u₁, . . . , u_(N) _(ldpc) ⁻¹).

The LDPC codeword parity-interleaved in the above-described method may be configured such that a predetermined number of continuous bits of the LDPC codeword have similar decoding characteristics (cycle distribution, a degree of a column, etc.).

For example, the LDPC codeword may have the same characteristics on the basis of M number of continuous bits. Herein, M is an interval at which a pattern of a column group is repeated in the information word submatrix 210 and, for example, may be 360.

Specifically, a product of the LDPC codeword bits and the parity check matrix should be “0”. This means that a sum of products of the i^(th) LDPC codeword bit, c_(i) (i=0, 1, . . . , N_(ldpc)−1) and the i^(th) column of the parity check matrix should be a “0” vector. Accordingly, the i^(th) LDPC codeword bit may be regarded as corresponding to the i^(th) column of the parity check matrix.

In the case of the parity check matrix 200 of FIG. 20, M number of columns in the information word submatrix 210 belong to the same group and the information word submatrix 210 has the same characteristics on the basis of a column group (for example, the columns belonging to the same column group have the same degree distribution and the same cycle characteristic).

In this case, since M number of continuous bits in the information word bits correspond to the same column group of the information word submatrix 210, the information word bits may be formed of M number of continuous bits having the same codeword characteristics. When the parity bits of the LDPC codeword are interleaved by the parity interleaver 121, the parity bits of the LDPC codeword may be formed of M number of continuous bits having the same codeword characteristics.

However, regarding the LDPC codeword encoded based on the parity check matrix 300 of FIG. 21 and the parity check matrix 400 of FIG. 22, parity interleaving may not be performed. In this case, the parity interleaver 121 may be omitted.

The group interleaver 122 may divide the parity-interleaved LDPC codeword into a plurality of bit groups and rearrange the order of the plurality of bit groups in bit group wise (or bit group unit). That is, the group interleaver 122 may interleave the plurality of bit groups in bit group wise.

To achieve this, the group interleaver 122 divides the parity-interleaved LDPC codeword into a plurality of bit groups by using Equation 19 or Equation 20 presented below.

$\begin{matrix} {X_{j} = {{\left\{ {{{u_{k\;}j} = \left\lfloor \frac{k}{360} \right\rfloor},{0 \leq k < N_{ldpc}}} \right\} \mspace{14mu} {for}\mspace{14mu} 0} \leq j < N_{group}}} & (19) \\ {{X_{j} = \left\{ {{u_{k}{{360 \times j} \leq k < {360 \times \left( {j + 1} \right)}}},{0 \leq k < N_{ldpc}}} \right\}}{{{for}\mspace{14mu} 0} \leq j < N_{group}}} & (20) \end{matrix}$

where N_(group) is the total number of bit groups, X_(j) is the j^(th) bit group, and u_(k) is the k^(th) LDPC codeword bit input to the group interleaver 122. In addition,

$\left\lfloor \frac{k}{360} \right\rfloor$

is the largest integer below k/360.

Since 360 in these equations indicates an example of the interval M at which the pattern of a column group is repeated in the information word submatrix, 360 in these equations can be changed to M.

The LDPC codeword which is divided into the plurality of bit groups may be as shown in FIG. 24.

Referring to FIG. 24, the LDPC codeword is divided into the plurality of bit groups and each bit group is formed of M number of continuous bits. When M is 360, each of the plurality of bit groups may be formed of 360 bits. Accordingly, the bit groups may be formed of bits corresponding to the column groups of the parity check matrix.

Specifically, since the LDPC codeword is divided by M number of continuous bits, K_(ldpc) number of information word bits are divided into (K_(ldpc)/M) number of bit groups and N_(ldpc)−K_(up), number of parity bits are divided into (N_(ldpc)−K_(ldpc))/M number of bit groups. Accordingly, the LDPC codeword may be divided into (N_(ldpc)/M) number of bit groups in total.

For example, when M=360 and the length N_(ldpc) of the LDPC codeword is 16200, the number of groups N_(groups) constituting the LDPC codeword is 45(=16200/360), and, when M=360 and the length N_(ldpc) of the LDPC codeword is 64800, the number of bit groups N_(group) constituting the LDPC codeword is 180(=64800/360).

As described above, the group interleaver 122 divides the LDPC codeword such that M number of continuous bits are included in a same group since the LDPC codeword has the same codeword characteristics on the basis of M number of continuous bits. Accordingly, when the LDPC codeword is grouped by M number of continuous bits, the bits having the same codeword characteristics belong to the same group.

In the above-described example, the number of bits constituting each bit group is M. However, this is merely an example and the number of bits constituting each bit group is variable.

For example, the number of bits constituting each bit group may be an aliquot part of M. That is, the number of bits constituting each bit group may be an aliquot part of the number of columns constituting a column group of the information word submatrix of the parity check matrix. In this case, each bit group may be formed of aliquot part of M number of bits. For example, when the number of columns constituting a column group of the information word submatrix is 360, that is, M=360, the group interleaver 122 may divide the LDPC codeword into a plurality of bit groups such that the number of bits constituting each bit group is one of the aliquot parts of 360.

In the following explanation, the number of bits constituting a bit group is M by way of an example, for the convenience of explanation.

Thereafter, the group interleaver 122 interleaves the LDPC codeword in bit group wise. Specifically, the group interleaver 122 may group the LDPC codeword into the plurality of bit groups and rearrange the plurality of bit groups in bit group wise. That is, the group interleaver 122 changes positions of the plurality of bit groups constituting the LDPC codeword and rearranges the order of the plurality of bit groups constituting the LDPC codeword in bit group wise.

Herein, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise such that bit groups including bits mapped onto the same modulation symbol from among the plurality of bit groups are spaced apart from one another at predetermined intervals.

In this case, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by considering at least one of the number of rows and columns of the block interleaver 124, the number of bit groups of the LDPC codeword, and the number of bits included in each bit group, such that bit groups including bits mapped onto the same modulation symbol are spaced apart from one another at predetermined intervals.

To achieve this, the group interleaver 122 may rearrange the order of the plurality of groups in bit group wise by using Equation 21 presented below:

Y _(j) =X _(π(j))(0≦J<N _(group))  (21),

where X_(j) is the j^(th) bit group before group interleaving, and Y_(j) is the j^(th) bit group after group interleaving. In addition, π(j) is a parameter indicating an interleaving order and is determined by at least one of a length of an LDPC codeword, a modulation method, and a code rate. That is, π(j) denotes a permutation order for group wise interleaving.

Accordingly, X_(π(j)) is a π(j)^(th) bit group before group interleaving, and Equation 21 means that the pre-interleaving η(j)^(th) bit group is interleaved into the j^(th) bit group.

According to an exemplary embodiment, an example of π(j) may be defined as in Tables 11 to 22 presented below.

In this case, π(j) is defined according to a length of an LPDC codeword and a code rate, and a parity check matrix is also defined according to a length of an LDPC codeword and a code rate. Accordingly, when LDPC encoding is performed based on a specific parity check matrix according to a length of an LDPC codeword and a code rate, the LDPC codeword may be interleaved in bit group wise based on π(j) satisfying the corresponding length of the LDPC codeword and code rate.

For example, when the encoder 110 performs LDPC encoding at a code rate of 6/15 to generate an LDPC codeword of a length of 64800, the group interleaver 122 may perform interleaving by using π(j) which is defined according to the length of the LDPC codeword of 16200 and the code rate of 6/15 in tables 11 to 22 presented below.

For example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method (or modulation format) is 16-Quadrature Amplitude Modulation (QAM), π(j) may be defined as in table 11 presented below. In particular, table 11 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 4.

In the case of Table 11, Equation 21 may be expressed as Y₀=X_(π(0))=X₅₅, Y₁=X_(π(1))=X₁₄₆, Y₂=X_(π(2))=X₈₃, . . . , Y₁₇₈=X_(π(178))=X₁₃₂, and Y₁₇₉=X_(π(179))=X₁₃₅. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 55^(th) bit group to the 0^(th) bit group, the 146^(th) bit group to the 1^(st) bit group, the 83^(rd) bit group to the 2^(nd) bit group, . . . , the 132^(nd) bit group to the 178^(th) bit group, and the 135^(th) bit group to the 179^(th) bit group. Herein, the changing the Ath bit group to the Bth bit group means rearranging the order of bit groups so that the Ath bit group is to be the Bth bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 16-QAM, π(j) may be defined as in table 12 presented below. In particular, table 12 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 5.

In the case of Table 12, Equation 21 may be expressed as Y₀=X_(π(0))=X₅₈, Y₁=X_(π(1))=X₅₅, Y₂=X_(π(2))=X₁₁₁, . . . , Y₁₇₈=X_(π(178))=X₁₇₁, and Y₁₇₉=X_(π(179))=X₁₅₅. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 58^(th) bit group to the 0^(th) bit group, the 55^(th) bit group to the 1^(st) bit group, the 111^(th) bit group to the 2^(nd) bit group, . . . , the 171^(st) bit group to the 178^(th) bit group, and the 155^(th) bit group to the 179^(th) bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 16-QAM, π(j) may be defined as in table 13 presented below. In particular, table 13 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 6.

In the case of Table 13, Equation 21 may be expressed as Y₀=X_(π(0))=X₇₄, Y₁=X_(π(1))=X₅₃, Y₂=X_(π(2))=X₈₄, . . . , Y₁₇₈=X_(π(178))=X₁₅₉, and Y₁₇₉=X_(π(179))=X₁₆₃. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 74^(th) bit group to the 0^(th) bit group, the 53^(rd) bit group to the 1^(st) bit group, the 84^(th) bit group to the 2^(nd) bit group, . . . , the 159^(th) bit group to the 178^(th) bit group, and the 163^(rd) bit group to the 179^(th) bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 16-QAM, π(j) may be defined as in table 14 presented below. In particular, table 14 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 7.

In the case of Table 14, Equation 21 may be expressed as Y₀=X_(π(0))=X₆₈, Y₁=X_(π(1))=X₇₁, Y₂=X_(π(2))=X₅₄, . . . , Y₁₇₈=X_(π(178))=X₁₃₅, and Y₁₇₉=X_(π(179))=X₂₄. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 68^(th) bit group to the 0^(th) bit group, the 71^(st) bit group to the 1^(st) bit group, the 54^(th) bit group to the 2^(nd) bit group, . . . , the 135^(th) bit group to the 178^(th) bit group, and the 24^(th) bit group to the 179^(th) bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 16-QAM, π(j) may be defined as in table 15 presented below. In particular, table 15 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 8.

In the case of Table 15, Equation 21 may be expressed as Y₀=X_(π(0))=X₁₂₀, Y₁=X_(π(1))=X₃₂, Y₂=X_(π(2))=X₃₈, . . . , Y₁₇₈=X_(π(178))=X₁₀₁, and Y₁₇₉=X_(π(179))=X₃₉. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 120^(th) bit group to the 0^(th) bit group, the 32^(nd) bit group to the 1^(st) bit group, the 38^(th) bit group to the 2^(nd) bit group, . . . , the 101^(st) bit group to the 178^(th) bit group, and the 39^(th) bit group to the 179^(th) bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 16-QAM, π(j) may be defined as in table 16 presented below. In particular, table 16 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 10.

In the case of Table 16, Equation 21 may be expressed as Y₀=X_(π(0))=X₁₆₃, Y₁=X_(π(1))=X₁₆₀, Y₂=X_(π(2))=X₁₃₈, . . . , Y₁₇₈=X_(π(178))=X₁₄₈, and Y₁₇₉=X_(π(179))=X₉₈. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 163^(rd) bit group to the 0^(th) bit group, the 160^(th) bit group to the 1^(st) bit group, the 138^(th) bit group to the 2^(nd) bit group, . . . , the 148^(th) bit group to the 178^(th) bit group, and the 98^(th) bit group to the 179^(th) bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 64-QAM, π(j) may be defined as in table 17 presented below. In particular, table 17 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 4.

In the case of Table 17, Equation 21 may be expressed as Y₀=X_(π(0))=X₂₉, Y₁=X_(π(1))=X₁₇, Y₂=X_(π(2))=X₃₈, . . . , Y₁₇₈=X_(π(178))=X₁₁₇, and Y₁₇₉=X_(π(179))=X₁₅₅. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 29^(th) bit group to the 0^(th) bit group, the 17^(th) bit group to the 1^(st) bit group, the 38^(th) bit group to the 2^(nd) bit group, . . . , the 117^(th) bit group to the 178^(th) bit group, and the 155^(th) bit group to the 179^(th) bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 8/15, and the modulation method is 64-QAM, π(j) may be defined as in table 18 presented below. In particular, table 18 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 5.

In the case of Table 18, Equation 21 may be expressed as Y₀=X_(π(0))=X₈₆, Y₁=X_(π(1))=X₇₁, Y₂=X_(π(2))=X₅₁, . . . , Y₁₇₈=X_(π(178))=X₁₇₄, and Y₁₇₉=X_(π(179))=X₁₂₈. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 86^(th) bit group to the 0^(th) bit group, the 71^(st) bit group to the 1^(st) bit group, the 51^(st) bit group to the 2^(nd) bit group, . . . , the 174^(th) bit group to the 178^(th) bit group, and the 128^(th) bit group to the 179^(th) bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 64-QAM, π(j) may be defined as in table 19 presented below. In particular, table 19 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 6.

In the case of Table 19, Equation 21 may be expressed as Y₀=X_(π(0))=X₇₃, Y₁=X_(π(1))=X₃₆, Y₂=X_(π(2))=X₂₁, . . . , Y₁₇₈=X_(π(178))=X₁₄₉, and Y₁₇₉=X_(π(179))=X₁₃₅. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 73^(rd) bit group to the 0^(th) bit group, the 36^(th) bit group to the 1^(st) bit group, the 21^(st) bit group to the 2^(nd) bit group, . . . , the 149^(th) bit group to the 178^(th) bit group, and the 135^(th) bit group to the 179^(th) bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 10/15, and the modulation method is 64-QAM, π(j) may be defined as in table 20 presented below. In particular, table 20 may be applied when LDPC encoding is performed ‘based on the parity check matrix defined by table 7.

In the case of Table 20, Equation 21 may be expressed as Y₀=X_(π(0))=X₁₁₃, Y₁=X_(π(1))=X₁₁₅, Y₂=X_(π(2))=X₄₇, . . . , Y₁₇₈=X_(π(178))=X₁₃₀, and Y₁₇₉=X_(π(179))=X₁₇₆. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 113^(th) bit group to the 0^(th) bit group, the 115^(th) bit group to the 1^(st) bit group, the 47^(th) bit group to the 2^(nd) bit group, . . . , the 130^(th) bit group to the 178^(th) bit group, and the 176^(th) bit group to the 179^(th) bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 12/15, and the modulation method is 64-QAM, π(j) may be defined as in table 21 presented below. In particular, table 21 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 8.

In the case of Table 21, Equation 21 may be expressed as Y₀=X_(π(0))=X₈₃, Y₁=X_(π(1)))=X₉₃, Y₂=X_(π(2))=X₉₄, . . . , Y₁₇₈=X_(π(178))=X₂, and Y₁₇₉=X_(π(179))=X₁₄. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 83^(rd) bit group to the 0^(th) bit group, the 93^(rd) bit group to the 1^(st) bit group, the 94^(th) bit group to the 2^(nd) bit group, . . . , the 2^(nd) bit group to the 178^(th) bit group, and the 14^(th) bit group to the 179^(th) bit group.

In another example, when the length of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is 64-QAM, π(j) may be defined as in table 22 presented below. In particular, table 22 may be applied when LDPC encoding is performed based on the parity check matrix defined by table 10.

In the case of Table 22, Equation 21 may be expressed as Y₀=X_(π(0))=X₁₇₅, Y₁=X_(π(1))=X₁₇₇, Y₂=X_(π(2))=X₁₇₃, . . . , Y₁₇₈=X_(π(178))=X₃₁, and Y₁₇₉=X_(π(179))=X₇₂. Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 175^(th) bit group to the 0^(th) bit group, the 177^(th) bit group to the 1^(st) bit group, the 173^(rd) bit group to the 2^(nd) bit group, . . . , the 31^(st) bit group to the 178^(th) bit group, and the 72^(nd) bit group to the 179^(th) bit group.

In the above-described examples, the length of the LDPC codeword is 64800 and the code rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and the interleaving pattern may be defined variously when the length of the LDPC codeword is 16200 or the code rate has different values.

As described above, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by using Equation 21 and Tables 11 to 22.

“j-th block of Group-wise Interleaver output” in tables 11 to 22 indicates the j-th bit group output from the group interleaver 122 after interleaving, and “π(j)-th block of Group-wise Interleaver input” indicates the π(j)-th bit group input to the group interleaver 122.

In addition, since the order of the bit groups constituting the LDPC codeword is rearranged by the group interleaver 122 in bit group wise, and then the bit groups are block-interleaved by the block interleaver 124, which will be described below, “Order of bit groups to be block interleaved” is set forth in Tables 11 to 22 in relation to π(j).

The LDPC codeword which is group-interleaved in the above-described method is illustrated in FIG. 25. Comparing the LDPC codeword of FIG. 25 and the LDPC codeword of FIG. 24 before group interleaving, it can be seen that the order of the plurality of bit groups constituting the LDPC codeword is rearranged.

That is, as shown in FIGS. 24 and 25, the groups of the LDPC codeword are arranged in order of bit group X₀, bit group X₁, . . . , bit group X_(Ngroup−1) before being group-interleaved, and are arranged in an order of bit group Y₀, bit group Y₁, . . . , bit group Y_(Ngroup−1) after being group-interleaved. In this case, the order of arranging the bit groups by the group interleaving may be determined based on Tables 11 to 22.

The group twist interleaver 123 interleaves bits in a same group. That is, the group twist interleaver 123 may rearrange the order of the bits in the same bit group by changing the order of the bits in the same bit group.

In this case, the group twist interleaver 123 may rearrange the order of the bits in the same bit group by cyclic-shifting a predetermined number of bits from among the bits in the same bit group.

For example, as shown in FIG. 26, the group twist interleaver 123 may cyclic-shift bits included in the bit group Y₁ to the right by 1 bit. In this case, the bits located in the 0^(th) position, the 1^(st) position, the 2^(nd) position, . . . , the 358^(th) position, and the 359^(th) position in the bit group Y₁ as shown in FIG. 26 are cyclic-shifted to the right by 1 bit. As a result, the bit located in the 359^(th) position before being cyclic-shifted is located in the front of the bit group Y₁ and the bits located in the 0^(th) position, the 1^(st) position, the 2^(nd) position, . . . , the 358^(th) position before being cyclic-shifted are shifted to the right serially by 1 bit and located.

In addition, the group twist interleaver 123 may rearrange the order of bits in each bit group by cyclic-shifting a different number of bits in each bit group.

For example, the group twist interleaver 123 may cyclic-shift the bits included in the bit group Y₁ to the right by 1 bit, and may cyclic-shift the bits included in the bit group Y₂ to the right by 3 bits.

However, the above-described group twist interleaver 123 may be omitted according to circumstances.

In addition, the group twist interleaver 123 is placed after the group interleaver 122 in the above-described example. However, this is merely an example. That is, the group twist interleaver 123 changes only the order of bits in a certain bit group and does not change the order of the bit groups. Therefore, the group twist interleaver 123 may be placed before the group interleaver 122.

The block interleaver 124 interleaves the plurality of bit groups the order of which has been rearranged. Specifically, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged by the group interleaver 122 in bit group wise (or bits group unit). The block interleaver 124 is formed of a plurality of columns each including a plurality of rows and may interleave by dividing the plurality of rearranged bit groups based on a modulation order determined according to a modulation method.

In this case, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged by the group interleaver 122 in bit group wise. Specifically, the block interleaver 124 may interleave by dividing the plurality of rearranged bit groups according to a modulation order by using a first part and a second part.

Specifically, the block interleaver 124 interleaves by dividing each of the plurality of columns into a first part and a second part, writing the plurality of bit groups in the plurality of columns of the first part serially in bit group wise, dividing the bits of the other bit groups into groups (or sub bit groups) each including a predetermined number of bits based on the number of columns, and writing the sub bit groups in the plurality of columns of the second part serially.

Herein, the number of bit groups which are interleaved in bit group wise may be determined by at least one of the number of rows and columns constituting the block interleaver 124, the number of bit groups and the number of bits included in each bit group. In other words, the block interleaver 124 may determine the bit groups which are to be interleaved in bit group wise considering at least one of the number of rows and columns constituting the block interleaver 124, the number of bit groups and the number of bits included in each bit group, interleave the corresponding bit groups in bit group wise, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups. For example, the block interleaver 124 may interleave at least part of the plurality of bit groups in bit group wise using the first part, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups using the second part.

Meanwhile, interleaving bit groups in bit group wise means that the bits included in the same bit group are written in the same column. In other words, the block interleaver 124, in case of bit groups which are interleaved in bit group wise, may not divide the bits included in the same bit groups and write the bits in the same column, and in case of bit groups which are not interleaved in bit group wise, may divide the bits in the bit groups and write the bits in different columns.

Accordingly, the number of rows constituting the first part is a multiple of the number of bits included in one bit group (for example, 360), and the number of rows constituting the second part may be less than the number of bits included in one bit group.

In addition, in all bit groups interleaved by the first part, the bits included in the same bit group are written and interleaved in the same column of the first part, and in at least one group interleaved by the second part, the bits are divided and written in at least two columns of the second part.

The specific interleaving method will be described later.

Meanwhile, the group twist interleaver 123 changes only the order of bits in the bit group and does not change the order of bit groups by interleaving. Accordingly, the order of the bit groups to be block-interleaved by the block interleaver 124, that is, the order of the bit groups to be input to the block interleaver 124, may be determined by the group interleaver 122. Specifically, the order of the bit groups to be block-interleaved by the block interleaver 124 may be determined by π(j) defined in Tables 11 to 22.

As described above, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged in bit group wise by using the plurality of columns each including the plurality of rows.

In this case, the block interleaver 124 may interleave the LDPC codeword by dividing the plurality of columns into at least two parts. For example, the block interleaver 124 may divide each of the plurality of columns into the first part and the second part and interleave the plurality of bit groups constituting the LDPC codeword.

In this case, the block interleaver 124 may divide each of the plurality of columns into N number of parts (N is an integer greater than or equal to 2) according to whether the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, and may perform interleaving.

When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 may interleave the plurality of bit groups constituting the LDPC codeword in bit group wise without dividing each of the plurality of columns into parts.

Specifically, the block interleaver 124 may interleave by writing the plurality of bit groups of the LDPC codeword on each of the columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

In this case, the block interleaver 124 may interleave by writing bits included in a predetermined number of bit groups, which corresponds to a quotient obtained by dividing the number of bit groups of the LDPC codeword by the number of columns of the block interleaver 124, on each of the plurality of columns serially in a column direction, and reading each row of the plurality of columns in which the bits are written in a row direction.

Hereinafter, the group located in the j^(th) position after being interleaved by the group interleaver 122 will be referred to as group Y₃.

For example, it is assumed that the block interleaver 124 is formed of C number of columns each including R₁ number of rows. In addition, it is assumed that the LDPC codeword is formed of N_(group) number of bit groups and the number of bit groups N_(group) is a multiple of C.

In this case, when the quotient obtained by dividing N_(group) number of bit groups constituting the LDPC codeword by C number of columns constituting the block interleaver 124 is A (=N_(group)/C) (A is an integer greater than 0), the block interleaver 124 may interleave by writing A (=N_(group)/C) number of bit groups on each column serially in a column direction and reading bits written on each column in a row direction.

For example, as shown in FIG. 27, the block interleaver 124 writes bits included in bit group Y₀, bit group Y₁, . . . , bit group Y_(A−1) in the 1^(st) column from the 1^(st) row to the R₁ ^(th) row, writes bits included in bit group Y_(A), bit group Y_(A+1), . . . , bit group Y_(2A−1) in the 2nd column from the 1^(st) row to the R₁ ^(th) row, . . . , and writes bits included in bit group Y_(CA-A) bit group Y_(CA-A+1), . . . , bit group Y_(CA−1) in the column C from the 1^(st) row to the R₁ ^(th) row. The block interleaver 124 may read the bits written in each row of the plurality of columns in a row direction.

Accordingly, the block interleaver 124 interleaves all bit groups constituting the LDPC codeword in bit group wise.

However, when the number of bit groups of the LDPC codeword is not an integer multiple of the number of columns of the block interleaver 124, the block interleaver 124 may divide each column into 2 parts and interleave a part of the plurality of bit groups of the LDPC codeword in bit group wise, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups. In this case, the bits included in the other bit groups, that is, the bits included in the number of groups which correspond to the remainder when the number of bit groups constituting the LDPC codeword is divided by the number of columns are not interleaved in bit group wise, but interleaved by being divided according to the number of columns.

Specifically, the block interleaver 124 may interleave the LDPC codeword by dividing each of the plurality of columns into two parts.

In this case, the block interleaver 124 may divide the plurality of columns into the first part and the second part based on at least one of the number of columns of the block interleaver 124, the number of bit groups of the LDPC codeword, and the number of bits of bit groups.

Here, each of the plurality of bit groups may be formed of 360 bits. In addition, the number of bit groups of the LDPC codeword is determined based on the length of the LDPC codeword and the number of bits included in the bit group. For example, when an LDPC codeword in the length of 16200 is divided such that each bit group has 360 bits, the LDPC codeword is divided into 45 bit groups. Alternatively, when an LDPC codeword in the length of 64800 is divided such that each bit group has 360 bits, the LDPC codeword may be divided into 180 bit groups. Further, the number of columns constituting the block interleaver 124 may be determined according to a modulation method. This will be explained in detail below.

Accordingly, the number of rows constituting each of the first part and the second part may be determined based on the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of bit groups.

Specifically, in each of the plurality of columns, the first part may be formed of as many rows as the number of bits included in at least one bit group which can be written in each column in bit group wise from among the plurality of bit groups of the LDPC codeword, according to the number of columns constituting the block interleaver 124, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each bit group.

In each of the plurality of columns, the second part may be formed of rows excluding as many rows as the number of bits included in at least some bit groups which can be written in each of the plurality of columns in bit group wise. Specifically, the number rows of the second part may be the same value as a quotient when the number of bits included in all bit groups excluding bit groups corresponding to the first part is divided by the number of columns constituting the block interleaver 124. In other words, the number of rows of the second part may be the same value as a quotient when the number of bits included in the remaining bit groups which are not written in the first part from among bit groups constituting the LDPC codeword is divided by the number of columns.

That is, the block interleaver 124 may divide each of the plurality of columns into the first part including as many rows as the number of bits included in bit groups which can be written in each column in bit group wise, and the second part including the other rows.

Accordingly, the first part may be formed of as many rows as the number of bits included in bit groups, that is, as many rows as an integer multiple of M. However, since the number of codeword bits constituting each bit group may be an aliquot part of M as described above, the first part may be formed of as many rows as an integer multiple of the number of bits constituting each bit group.

In this case, the block interleaver 124 may interleave by writing and reading the LDPC codeword in the first part and the second part in the same method.

Specifically, the block interleaver 124 may interleave by writing the LDPC codeword in the plurality of columns constituting each of the first part and the second part in a column direction, and reading the plurality of columns constituting the first part and the second part in which the LDPC codeword is written in a row direction.

That is, the block interleaver 124 may interleave by writing the bits included in at least some bit groups which can be written in each of the plurality of columns in bit group wise in each of the plurality of columns of the first part serially, dividing the bits included in the other bit groups except the at least some bit groups and writing in each of the plurality of columns of the second part in a column direction, and reading the bits written in each of the plurality of columns constituting each of the first part and the second part in a row direction.

In this case, the block interleaver 124 may interleave by dividing the other bit groups except the at least some bit groups from among the plurality of bit groups based on the number of columns constituting the block interleaver 124.

Specifically, the block interleaver 124 may interleave by dividing the bits included in the other bit groups by the number of a plurality of columns, writing each of the divided bits in each of a plurality of columns constituting the second part in a column direction, and reading the plurality of columns constituting the second part, where the divided bits are written, in a row direction.

That is, the block interleaver 124 may divide the bits included in the other bit groups except the bit groups written in the first part from among the plurality of bit groups of the LDPC codeword, that is, the bits in the number of bit groups which correspond to the remainder when the number of bit groups constituting the LDPC codeword is divided by the number of columns, by the number of columns, and may write the divided bits in each column of the second part serially in a column direction.

For example, it is assumed that the block interleaver 124 is formed of C number of columns each including R₁ number of rows. In addition, it is assumed that the LDPC codeword is formed of N_(group) number of bit groups, the number of bit groups N_(group) is not a multiple of C, and A×C+1=N_(group) (A is an integer greater than 0). In other words, it is assumed that when the number of bit groups constituting the LDPC codeword is divided by the number of columns, the quotient is A and the remainder is 1.

In this case, as shown in FIGS. 28 and 29, the block interleaver 124 may divide each column into a first part including R₁ number of rows and a second part including R₂ number of rows. In this case, R₁ may correspond to the number of bits included in bit groups which can be written in each column in bit group wise, and R₂ may be R₁ subtracted from the number of rows of each column.

That is, in the above-described example, the number of bit groups which can be written in each column in bit group wise is A, and the first part of each column may be formed of as many rows as the number of bits included in A number of bit groups, that is, may be formed of as many rows as A×M number.

In this case, the block interleaver 124 writes the bits included in the bit groups which can be written in each column in bit group wise, that is, A number of bit groups, in the first part of each column in the column direction.

That is, as shown in FIGS. 28 and 29, the block interleaver 124 writes the bits included in each of bit group Y₀, bit group Y₁, . . . , group Y_(A−1) in the 1^(st) to R₁ ^(th) rows of the first part of the 1^(st) column, writes bits included in each of bit group Y_(A), bit group Y_(A+1), . . . , bit group Y_(2A−1) in the 1^(st) to R₁ ^(th) rows of the first part of the 2^(nd) column, . . . , writes bits included in each of bit group Y_(CA-A), bit group Y_(CA-A+1), . . . , bit group Y_(CA-1) in the 1^(st) to R₁ ^(th) rows of the first part of the column C.

As described above, the block interleaver 124 writes the bits included in the bit groups which can be written in each column in bit group wise in the first part of each column.

In other words, in the above exemplary embodiment, the bits included in each of bit group (Y₀), bit group (Y₁), . . . , bit group (Y_(A−1)) may not be divided and all of the bits may be written in the first column, the bits included in each of bit group (Y_(A)), bit group (Y_(A+1)), . . . , bit group (Y_(2A−1)) may not be divided and all of the bits may be written in the second column, and the bits included in each of bit group (Y_(CA-A)), bit group (Y_(CA-A+1)), . . . , group (Y_(CA−1)) may not be divided and all of the bits may be written in the C column. As such, all bit groups interleaved by the first part are written in the same column of the first part.

Thereafter, the block interleaver 124 divides bits included in the other bit groups except the bit groups written in the first part of each column from among the plurality of bit groups, and writes the bits in the second part of each column in the column direction. In this case, the block interleaver 124 divides the bits included in the other bit groups except the bit groups written in the first part of each column by the number of columns, so that the same number of bits are written in the second part of each column, and writes the divided bits in the second part of each column in the column direction.

In the above-described example, since A×C+1=N_(group), when the bit groups constituting the LDPC codeword are written in the first part serially, the last bit group Y_(Ngroup−1) of the LDPC codeword is not written in the first part and remains. Accordingly, the block interleaver 124 divides the bits included in the bit group Y_(Ngroup−1) into C number of sub bit groups as shown in FIG. 28, and writes the divided bits (that is, the bits corresponding to the quotient when the bits included in the last group (Y_(Ngroup−1)) are divided by C) in the second part of each column serially.

The bits divided based on the number of columns may be referred to as sub bit groups. In this case, each of the sub bit groups may be written in each column of the second part. That is, the bits included in the bit groups may be divided and may form the sub bit groups.

That is, the block interleaver 124 writes the bits in the 1^(st) to R₂ ^(th) rows of the second part of the 1^(st) column, writes the bits in the 1^(st) to R₂ ^(th) rows of the second part of the 2^(nd) column, . . . , and writes the bits in the 1^(st) to R₂ ^(th) rows of the second part of the column C. In this case, the block interleaver 124 may write the bits in the second part of each column in the column direction as shown in FIG. 28.

That is, in the second part, the bits constituting the bit group may not be written in the same column and may be written in the plurality of columns. In other words, in the above example, the last bit group (Y_(Ngroup−1)) is formed of M number of bits and thus, the bits included in the last bit (Y_(Ngroup−1)) group may be divided by M/C and written in each column. That is, the bits included in the last bit group (Y_(Ngroup−1)) are divided by M/C, forming M/C number of sub bit groups, and each of the sub bit groups may be written in each column of the second part.

Accordingly, in at least one bit group which is interleaved by the second part, the bits included in the at least one bit group are divided and written in at least two columns constituting the second part.

In the above-described example, the block interleaver 124 writes the bits in the second part in the column direction. However, this is merely an example. That is, the block interleaver 124 may write the bits in the plurality of columns of the second part in the row direction. In this case, the block interleaver 124 may write the bits in the first part in the same method as described above.

Specifically, referring to FIG. 29, the block interleaver 124 writes the bits from the 1^(st) row of the second part in the 1^(st) column to the 1^(st) row of the second part in the column C, writes the bits from the 2^(nd) row of the second part in the 1^(st) column to the 2^(nd) row of the second part in the column C, . . . , etc., and writes the bits from the R₂ ^(th) row of the second part in the 1^(st) column to the R₂ ^(th) row of the second part in the column C.

On the other hand, the block interleaver 124 reads the bits written in each row of each part serially in the row direction. That is, as shown in FIGS. 28 and 29, the block interleaver 124 reads the bits written in each row of the first part of the plurality of columns serially in the row direction, and reads the bits written in each row of the second part of the plurality of columns serially in the row direction.

Accordingly, the block interleaver 124 may interleave a part of the plurality of bit groups constituting the LDPC codeword in bit group wise, and divide and interleave some of the remaining bit groups. That is, the block interleaver 124 may interleave by writing the LDPC codeword constituting a predetermined number of bit groups from among the plurality of bit groups in the plurality of columns of the first part in bit group wise, dividing the bits of the other bit groups and writing the bits in each of the columns of the second part, and reading the plurality of columns of the first and second parts in the row direction.

As described above, the block interleaver 124 may interleave the plurality of bit groups in the methods described above with reference to FIGS. 27 to 29.

In particular, in the case of FIG. 28, the bits included in the bit group which does not belong to the first part are written in the second part in the column direction and read in the row direction. In view of this, the order of the bits included in the bit group which does not belong to the first part is rearranged. Since the bits included in the bit group which does not belong to the first part are interleaved as described above, bit rrror rate (BER)/frame error rate (FER) performance can be improved in comparison with a case in which such bits are not interleaved.

However, the bit group which does not belong to the first part may not be interleaved as shown in FIG. 29. That is, since the block interleaver 124 writes and reads the bits included in the group which does not belong to the first part in and from the second part in the row direction, the order of the bits included in the group which does not belong to the first part is not changed and the bits are output to the modulator 130 serially. In this case, the bits included in the group which does not belong to the first part may be output serially and mapped onto a modulation symbol.

In FIGS. 28 and 29, the last single bit group of the plurality of bit groups is written in the second part. However, this is merely an example. The number of bit groups written in the second part may vary according to the total number of bit groups of the LDPC codeword, the number of columns and rows, the number of transmission antennas, etc.

The block interleaver 124 may have a configuration as shown in tables 23 and 24 presented below:

TABLE 23 N_(Idpc) = 64800 QPSK 16 QAM 64 QAM 256 QAM 1024 QAM 4096 QAM C 2 4 6 8 10 12 R₁ 32400 16200 10800 7920 6480 5400 R₂ 0 0 0 180 0 0

TABLE 24 N_(Idpc) = 16200 QPSK 16 QAM 64 QAM 256 QAM 1024 QAM 4096 QAM C 2 4 6 8 10 12 R₁ 7920 3960 2520 1800 1440 1080 R₂ 180 90 180 225 180 270

Herein, C (or NO is the number of columns of the block interleaver 124, R₁ is the number of rows constituting the first part in each column, and R₂ is the number of rows constituting the second part in each column.

Referring to Tables 23 and 24, the number of columns has the same value as a modulation order according to a modulation method, and each of a plurality of columns is formed of rows corresponding to the number of bits constituting the LDPC codeword divided by the number of a plurality of columns.

For example, when the length N_(ldpc) of the LDPC codeword is 64800 and the modulation method is 16-QAM, the block interleaver 124 is formed of 4 columns as the modulation order is 4 in the case of 16-QAM, and each column is formed of rows as many as R₁+R₂=16200(=64800/4). In another example, when the length N_(ldpc) of the LDPC codeword is 64800 and the modulation method is 64-QAM, the block interleaver 124 is formed of 6 columns as the modulation order is 6 in the case of 64-QAM, and each column is formed of rows as many as R₁+R₂=10800(=64800/6).

Meanwhile, referring to Tables 23 and 24, when the number of bit groups constituting an LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 interleaves without dividing each column. Therefore, R₁ corresponds to the number of rows constituting each column, and R₂ is 0. In addition, when the number of bit groups constituting an LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 interleaves the groups by dividing each column into the first part formed of R₁ number of rows, and the second part formed of R₂ number of rows.

When the number of columns of the block interleaver 124 is equal to the number of bits constituting a modulation symbol, bits included in a same bit group are mapped onto a single bit of each modulation symbol as shown in Tables 23 and 24.

For example, when N_(ldpc)=64800 and the modulation method is 16-QAM, the block interleaver 124 may be formed of four (4) columns each including 16200 rows. In this case, the bits included in each of the plurality of bit groups are written in the four (4) columns and the bits written in the same row in each column are output serially. In this case, since four (4) bits constitute a single modulation symbol in the modulation method of 16-QAM, bits included in the same bit group, that is, bits output from a single column, may be mapped onto a single bit of each modulation symbol. For example, bits included in a bit group written in the 1^(st) column may be mapped onto the first bit of each modulation symbol.

In another example, when N_(ldpc)=64800 and the modulation method is 64-QAM, the block interleaver 124 may be formed of six (6) columns each including 10800 rows. In this case, the bits included in each of the plurality of bit groups are written in the six (6) columns and the bits written in the same row in each column are output serially. In this case, since six (6) bits constitute a single modulation symbol in the modulation method of 64-QAM, bits included in the same bit group, that is, bits output from a single column, may be mapped onto a single bit of each modulation symbol. For example, bits included in a bit group written in the 1^(st) column may be mapped onto the first bit of each modulation symbol.

Referring to Tables 23 and 24, the total number of rows of the block interleaver 124, that is, R₁+R₂, is N_(ldpc)/C.

In addition, the number of rows of the first part, R₁, is an integer multiple of the number of bits included in each group, M (e.g., M=360), and maybe expressed as └N_(group)/C┘×M, and the number of rows of the second part, R₂, may be N_(ldpc)/C−R₁. Herein, └N_(group)/C┘ is the largest integer below N_(group)/C. Since R₁ is an integer multiple of the number of bits included in each group, M, bits may be written in R₁ in bit groups wise.

In addition, when the number of bit groups of the LDPC codeword is not a multiple of the number of columns, it can be seen from Tables 23 and 24 that the block interleaver 124 interleaves by dividing each column into two parts.

Specifically, the length of the LDPC codeword divided by the number of columns is the total number of rows included in the each column. In this case, when the number of bit groups of the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, when the number of bit groups of the LDPC codeword is not a multiple of the number of columns, each column is divided into two parts.

For example, it is assumed that the number of columns of the block interleaver 124 is identical to the number of bits constituting a modulation symbol, and an LDPC codeword is formed of 64800 bits as shown in Table 28. In this case, each bit group of the LDPC codeword is formed of 360 bits, and the LDPC codeword is formed of 64800/360(=180) bit groups.

When the modulation method is 16-QAM, the block interleaver 124 may be formed of four (4) columns and each column may have 64800/4(=16200) rows.

In this case, since the number of bit groups of the LDPC codeword divided by the number of columns is 180/4(=45), bits can be written in each column in bit group wise without dividing each column into two parts. That is, bits included in 45 bit groups which is the quotient when the number of bit groups constituting the LDPC codeword is divided by the number of columns, that is, 45×360(=16200) bits can be written in each column.

However, when the modulation method is 256-QAM, the block interleaver 124 may be formed of eight (8) columns and each column may have 64800/8(=8100) rows.

In this case, since the number of bit groups of the LDPC codeword divided by the number of columns is 180/8=22.5, the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns. Accordingly, the block interleaver 124 divides each of the eight (8) columns into two parts to perform interleaving in bit group wise.

In this case, since the bits should be written in the first part of each column in bit group wise, the number of bit groups which can be written in the first part of each column in bit group wise is 22, which is the quotient when the number of bit groups constituting the LDPC codeword is divided by the number of columns, and accordingly, the first part of each column has 22×360(=7920) rows. Accordingly, 7920 bits included in 22 bit groups may be written in the first part of each column.

The second part of each column has rows which are the rows of the first part subtracted from the total rows of each column. Accordingly, the second part of each column includes 8100−7920(=180) rows.

In this case, the bits included in the other bit groups which have not been written in the first part are divided and written in the second part of each column.

Specifically, since 22×8(=176) bit groups are written in the first part, the number of bit groups to be written in the second part is 180−176 (=4) (for example, bit group Y₁₇₆, bit group Y₁₇₇, bit group Y₁₇₈, and bit group Y₁₇₉ from among bit group Y₀, bit group Y₁, bit group Y₂, . . . , bit group Y₁₇₈, and bit group Y₁₇₉ constituting the LDPC codeword).

Accordingly, the block interleaver 124 may write the four (4) bit groups which have not been written in the first part and remains from among the groups constituting the LDPC codeword in the second part of each column serially.

That is, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y₁₇₆ in the 1^(st) row to the 180^(th) row of the second part of the 1^(st) column in the column direction, and may write the other 180 bits in the 1^(st) row to the 180^(th) row of the second part of the 2^(nd) column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y₁₇₇ in the 1^(st) row to the 180^(th) row of the second part of the 3^(rd) column in the column direction, and may write the other 180 bits in the 1^(st) row to the 180^(th) row of the second part of the 4^(th) column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y₁₇₈ in the 1^(st) row to the 180^(th) row of the second part of the 5^(th) column in the column direction, and may write the other 180 bits in the 1^(st) row to the 180^(th) row of the second part of the 6^(th) column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y₁₇₉ in the 1^(st) row to the 180^(th) row of the second part of the 7^(th) column in the column direction, and may write the other 180 bits in the 1^(st) row to the 180^(th) row of the second part of the 8^(th) column in the column direction.

Accordingly, the bits included in the bit group which has not been written in the first part and remains are not written in the same column in the second part and may be divided and written in the plurality of columns.

Hereinafter, the block interleaver 124 of FIG. 23 according to an exemplary embodiment will be explained in detail with reference to FIG. 30.

In a group-interleaved LDPC codeword (v₀, v₁, . . . , v_(N) _(ldpc) ⁻¹), Y_(j) is continuously arranged like V={Y₀, Y₁, . . . Y_(N) _(group) ⁻¹}.

The LDPC codeword after group interleaving may be interleaved by the block interleaver 124 as shown in FIG. 30. In this case, the block interleaver 124 divide a plurality of columns into the first part (Part 1) and the second part (Part 2) based on the number of columns of the block interleaver 124 and the number of bits of bit groups. In this case, in the first part, the bits constituting the bit groups may be written in the same column, and in the second part, the bits constituting the bit groups may be written in a plurality of columns (i.e. the bits constituting the bit groups may be written in at least two columns).

Specifically, input bits vi are written serially from the first part to the second part column wise, and then read out serially from the first part to the second part row wise. That is, the data bits v_(i) are written serially into the block interleaver column-wise starting in the first aprt and continuing column-wise finishing in the second part, and then read out serially row-wise from the first part and then row-wise from the second part. Accordingly, the bit included in the same bit group in the first part may be mapped onto a single bit of each modulation symbol.

In this case, the number of columns and the number of rows of the first part and the second part of the block interleaver 124 vary according to a modulation format and a length of the LDPC codeword as in Table 25 presented below. That is, the first part and the second part block interleaving configurations for each modulation format and code length are specified in Table 25 presented below. Herein, the number of columns of the block interleaver 124 may be equal to the number of bits constituting a modulation symbol. In addition, a sum of the number of rows of the first part, N_(r1) and the number of rows of the second part, N_(r2), is equal to N_(ldpc)/N_(C) (herein, N_(C) is the number of columns). In addition, since N_(r1)(=└N_(group)/N_(c)┘×360) is a multiple of 360, a multiple of bit groups may be written in the first part.

TABLE 25 Rows in Part 1 N_(r1) Rows in Part 2 N_(r2) N_(ldpc) = N_(ldpc) = N_(ldpc) = N_(ldpc) = Columns Modulation 64800 16200 64800 16200 N_(c) QPSK 32400 7920 0 180 2 16-QAM 16200 3960 0 90 4 64-QAM 10800 2520 0 180 6 256-QAM 7920 1800 180 225 8 1024-QAM 6480 1440 0 180 10 4096-QAM 5400 1080 0 270 12

Hereinafter, an operation of the block interleaver 124 will be explained in detail.

Specifically, as shown in FIG. 30, the input bit v_(i) (0≦i<N_(C)×N_(r1)) is written in r_(i) row of c_(i) column of the first part of the block interleaver 124. Herein, c_(i) and r_(i) are

$c_{i} = \left\lfloor \frac{i}{N_{r\; 1}} \right\rfloor$

and r₁=(i mod N_(r1)), respectively.

In addition, the input bit v_(i) (N_(C)×N_(r1)≦i<N_(ldpc)) is written in r_(i) row of c_(i) column of the second part of the block interleaver 124. Herein, c_(i) and r_(i) satisfy

$c_{i} = \left\lfloor \frac{\left( {i - {N_{C} \times N_{r\; 1}}} \right)}{N_{r\; 2}} \right\rfloor$

and r_(i)=N_(r1)+{(i−N_(C)×N_(r1))mod N_(r2)}, respectively.

An output bit q_(j)(0≦j<N_(ldpc)) is read from c_(j) column of r_(j) row. Herein, r_(j) and c_(j) satisfy

$r_{j} = \left\lfloor \frac{j}{N_{c}} \right\rfloor$

and c_(j)=(j mod N_(C)), respectively.

For example, when the length N_(ldpc) of an LDPC codeword is 64800 and the modulation method is 256-QAM, the order of bits output from the block interleaver 124 may be (q₀, q₁, q₂, . . . , q₆₃₃₅₇, q₆₃₃₅₈, q₆₃₃₅₉, q₆₃₃₆₀, q₆₃₃₆₁, . . . , q₆₄₇₉₉)=(v₀, v₇₉₂₀, v₁₅₈₄₀, . . . , v₄₇₅₁₉, v₅₅₄₃₉, v₆₃₃₅₉, v₆₃₃₆₀, v₆₃₅₄₀, . . . , v₆₄₇₉₉). Herein, the indexes of the right side of the foregoing equation may be specifically expressed for the eight (8) columns as 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441, . . . , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, . . . , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.

Hereinafter, the interleaving operation of the block interleaver 124 will be explained in detail.

The block interleaver 124 may interleave by writing a plurality of bit groups in each column in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

In this case, the number of columns constituting the block interleaver 124 may vary according to a modulation method, and the number of rows may be the length of the LDPC codeword/the number of columns.

For example, when the modulation method is 16-QAM, the block interleaver 124 may be formed of 4 columns. In this case, when the length N_(ldpc) of the LDPC codeword is 16200, the number of rows is 16200 (=64800/4). In another example, when the modulation method is 64-QAM, the block interleaver 124 may be formed of 6 columns. In this case, when the length N_(ldpc) of the LDPC codeword is 64800, the number of rows is 10800 (=64800/6).

Hereinafter, the method for interleaving the plurality of bit groups in bit group wise by the block interleaver 124 will be explained in detail.

When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 may interleave by writing the bit groups as many as the number of bit groups divided by the number of columns in each column serially in bit group wise.

For example, when the modulation method is 16-QAM and the length N_(ldpc) of the LDPC codeword is 64800, the block interleaver 124 may be formed of four (4) columns each including 16200 rows. In this case, since the LDPC codeword is divided into (64800/360=180) number of bit groups when the length N_(ldpc) of the LDPC codeword is 64800, the number of bit groups (=180) of the LDPC codeword may be an integer multiple of the number of columns (=4) when the modulation method is 16-QAM. That is, no remainder is generated when the number of bit groups of the LDPC codeword is divided by the number of columns.

In this case, as shown in FIG. 31, the block interleaver 124 writes the bits included in each of the bit group Y₀, bit group Y₁, . . . , bit group Y₄₄ in the 1^(st) row to 16200^(th) row of the first column, writes the bits included in each of the bit group Y₄₅, the bit group Y₄₆, . . . , the bit group Y₈₉ in the 1^(st) row to 16200^(th) row of the second column, writes the bits included in each of the bit group Y₉₀, the bit group Y₉₁, . . . , the bit group Y₁₃₄ in the 1^(st) row to 16200^(th) row of the third column, and writes the bits included in each of the bit group Y₁₃₅, the bit group Y₁₃₆, . . . , the bit group Y₁₇₉ in the 1^(st) row to 16200^(th) row of the fourth column. In addition, the block interleaver 124 may read the bits written in each row of the two columns serially in the row direction.

In another, when the modulation method is 64-QAM and the length N_(ldpc) of the LDPC codeword is 64800, the block interleaver 124 may be formed of six (6) columns each including 10800 rows. In this case, since the LDPC codeword is divided into (64800/360=180) number of bit groups when the length N_(ldpc) of the LDPC codeword is 64800, the number of bit groups (=180) of the LDPC codeword may be an integer multiple of the number of columns (=4) when the modulation method is 64-QAM. That is, no remainder is generated when the number of bit groups of the LDPC codeword is divided by the number of columns.

In this case, as shown in FIG. 32, the block interleaver 124 writes the bits included in each of the bit group Y₀, bit group Y₁, . . . , bit group Y₂₉ in the 1^(st) row to 10800^(th) row of the first column, writes the bits included in each of the bit group Y₃₀, the bit group Y₃₁, . . . , the bit group Y₅₉ in the 1^(st) row to 10800^(th) row of the second column, writes the bits included in each of the bit group Y₆₀, the bit group Y₆₁, . . . , the bit group Y₈₉ in the 1^(st) row to 10800^(th) row of the third column, writes the bits included in each of the bit group Y₉₀, the bit group Y₉₁, . . . , the bit group Y₁₁₉ in the 1^(st) row to 10800^(th) row of the fourth column, writes the bits included in each of the bit group Y₁₂₀, the bit group Y₁₂₁, . . . , the bit group Y₁₄₉ in the 1^(st) row to 10800^(th) row of the fifth column, and writes the bits included in each of the bit group Y₁₅₀, the bit group Y₁₅₁, . . . , the bit group Y₁₇₉ in the 1^(st) row to 10800^(th) row of the sixth column. In addition, the block interleaver 124 may read the bits written in each row of the two columns serially in the row direction.

As described above, when the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns of the block interleaver 124, the block interleaver 124 may interleave the plurality of bit groups in bit group wise, and accordingly, the bits belonging to the same bit group may be written in the same column.

As described above, the block interleaver 124 may interleave the plurality of bit groups of the LDPC codeword in the method described above with reference to FIGS. 31 and 32.

The modulator 130 maps the interleaved LDPC codeword onto a modulation symbol. Specifically, the modulator 130 may demultiplex the interleaved LDPC codeword, modulate the demultiplexed LDPC codeword, and map the LDPC codeword onto a constellation.

In this case, the modulator 130 may generate a modulation symbol using the bits included in each of a plurality of bit groups.

In other words, as described above, the bits included in different bit groups are written in each column of the block interleaver 124, and the block interleaver 124 reads the bits written in each column in the row direction. In this case, the modulator 130 generates a modulation symbol by mapping the bits read in each column onto each bit of the modulation symbol. Accordingly, each bit of the modulation symbol belongs to a different bit group.

For example, it is assumed that the modulation symbol consists of C number of bits. In this case, the bits which are read from each row of C number of columns of the block interleaver 124 may be mapped onto each bit of the modulation symbol and thus, each bit of the modulation symbol consisting of C number of bits belong to C number of different bit groups.

Hereinbelow, the above feature will be described in greater detail.

First, the modulator 130 demultiplexes the interleaved LDPC codeword. To achieve this, the modulator 130 may include a demultiplexer (not shown) to demultiplex the interleaved LDPC codeword.

The demultiplexer (not shown) demultiplexes the interleaved LDPC codeword. Specifically, the demultiplexer (not shown) performs serial-to-parallel conversion with respect to the interleaved LDPC codeword, and demultiplexes the interleaved LDPC codeword into a cell having a predetermined number of bits (or a data cell).

For example, as shown in FIG. 33, the demultiplexer (not shown) receives the LDPC codeword Q=(q₀, q₁, q₂, . . . ) output from the interleaver 120, outputs the received LDPC codeword bits to a plurality of substreams serially, converts the input LDPC codeword bits into cells, and outputs the cells.

In this case, the bits having the same index in each of the plurality of substreams may constitute the same cell. Accordingly, the cells may be configured like (y_(0,0), y_(1,0), . . . , y_(η MOD−1,0))=(q₀, q₁, q_(η MOD−1)), (y_(0,1), y_(1,1), . . . , yη_(MOD−1,1))=(q_(η MOD), q_(η MOD+1), . . . , q_(2×η MOD−1)), . . . .

Herein, the number of substreams, N_(substreams), may be equal to the number of bits constituting a modulation symbol, η_(MOD). Accordingly, the number of bits constituting each cell may be equal to the number of bits constituting a modulation symbol (that is, a modulation order).

For example, when the modulation method is 16-QAM, the number of bits constituting the modulation symbol, η_(MOD), is 4 and thus the number of substreams, N_(substreams), is 4, and the cells may be configured like (y_(0,0), y_(1,0), y_(2,0), y_(3,0))=(q₀, q₁, q₂, q₃), (y_(0,1), y_(1,1), y_(2,1), y_(3,1))=(q₄, q₅, q₆, q₇), (y_(0,2), Y_(1,2), y_(2,2), y_(3,2))=(q₈, q₉, q₁₀, q₁₁), . . . .

In another example, when the modulation method is 64-QAM, the number of bits constituting the modulation symbol, η_(MOD), is 6 and thus the number of substreams, N_(substreams), is 6, and the cells may be configured like (y_(0,0), y_(1,0), y_(2,0), y_(3,0), y_(4,0), y_(5,0))=(q₀, q₁, q₂, q₃, q₄, q₅), (y_(0,1), y_(1,1), Y_(2,1), y_(3,1), y_(4,1), y_(5,1))=(q₆,q₇, q₈,q₉, q₁₀,q₁₁), (y_(0,2), Y_(1,2), y_(2,2), y_(3,2), y_(4,2), Y_(5,2))=(q₁₂, q₁₃, q₁₄, q₁₅, q₁₆, q₁₇), . . . .

The modulator 130 may map the demultiplexed LDPC codeword onto modulation symbols.

Specifically, the modulator 130 may modulate bits (that is, cells) output from the demultiplexer (not shown) in various modulation methods such as Quadrature Phase Shift Keying (QPSK), 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, etc. For example, when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, the number of bits constituting the modulation symbol, η_(MOD) (that is, the modulation order), may be 2, 4, 6, 8, 10 and 12, respectively.

In this case, since each cell output from the demultiplexer (not shown) is formed of as many bits as the number of bits constituting the modulation symbol, the modulator 130 may generate the modulation symbol by mapping each cell output from the demultiplexer (not shown) onto a constellation point serially. Herein, the modulation symbol corresponds to a constellation point on the constellation.

However, the above-described demultiplexer (not shown) may be omitted according to circumstances. In this case, the modulator 130 may generate modulation symbols by grouping a predetermined number of bits from interleaved bits serially and mapping the predetermined number of bits onto constellation points. In this case, the modulator 130 may generate the modulation symbols by mapping η_(MOD) number of bits onto the constellation points serially according to a modulation method.

The modulator 130 may modulate by mapping cells output from the demultiplexer (not shown) onto constellation points in a non-uniform constellation (NUC) method.

In the non-uniform constellation method, once a constellation point of the first quadrant is defined, constellation points in the other three quadrants may be determined as follows. For example, when a set of constellation points defined for the first quadrant is X, the set becomes −conj(X) in the case of the second quadrant, becomes conj(X) in the case of the third quadrant, and becomes −(X) in the case of the fourth quadrant.

That is, once the first quadrant is defined, the other quadrants may be expressed as follows:

-   -   1 Quarter (first quadrant)=X     -   2 Quarter (second quadrant)=−conj(X)     -   3 Quarter (third quadrant)=conj(X)     -   4 Quarter (fourth quadrant)=−X

Specifically, when the non-uniform M-QAM is used, M number of constellation points may be defined as z={z₀, z₁, . . . z_(M−1)}. In this case, when the constellation points existing in the first quadrant are defined as {x₀, x₁, x₂, . . . , x_(M/4−1)}, z may be defined as follows:

-   -   from z₀ to z_(M/4−1)=from x₀ to x_(M/4)     -   from z_(M/4) to z_(2×M/4−1)=−conj(from x₀ to x_(M/4))     -   from z_(2×M/4) to z_(3×M/4−1)=conj(from x₀ to x_(M/4))     -   from z_(3×M/4) to z_(4×M/4−1)=−(from x₀ to x_(M/4))

Accordingly, the modulator 130 may map the bits [y₀, . . . , y_(m−1)] output from the demultiplexer (not shown) onto constellation points in the non-uniform constellation method by mapping the output bits onto z_(L) having an index of

$L = {\sum\limits_{i = 0}^{m - 1}{\left( {y_{1} \times 2^{m - 1}} \right).}}$

An example of the constellation defined according to the non-uniform constellation method may be expressed as in tables 26 to 30 presented below when the code rate is 5/15, 7/15, 9/15, 11/15, 13/15:

TABLE 26 Input data cell y Constellation point Z_(s) (00)  (1 + 1i)/{square root over (2)} (01)  (1 − 1i)/{square root over (2)} (10) (−1 + 1i)/{square root over (2)} (11) (−1 − 1i)/{square root over (2)}

TABLE 27 w/Shape NUC_16_6/15 NUC_16_7/15 NUC_16_8/15 NUC_16_9/15 w0 0.4530 + 0.2663i 1.2103 + 0.5026i 0.4819 + 0.2575i 0.4909 + 1.2007i w1 0.2663 + 0.4530i 0.5014 + 1.2103i 0.2575 + 0.4819i 1.2007 + 0.4909i w2 1.2092 + 0.5115i 0.4634 + 0.2624i 1.2068 + 0.4951i 0.2476 + 0.5065i w3 0.5115 + 1.2092i 0.2624 + 0.4627i 0.4951 + 1.2068i 0.5053 + 0.2476i w/Shape NUC_16_10/15 NUC_16_11/15 NUC_16_12/15 NUC_16_13/15 w0 0.2173 + 0.4189i 0.9583 + 0.9547i 0.2999 + 0.2999i 0.9517 + 0.9511i w1 0.6578 + 0.2571i 0.9547 + 0.2909i 0.9540 + 0.2999i 0.9524 + 0.3061i w2 0.4326 + 1.1445i 0.2921 + 0.9583i 0.2999 + 0.9540i 0.3067 + 0.9524i w3 1.2088 + 0.5659i 0.2909 + 0.2927i 0.9540 + 0.9540i 0.3061 + 0.3067i

TABLE 28 x/Shape R64_6/15 R64_7/15 R64_8/15 R64_9/15 x0 0.4387 + 1.6023i 0.3352 + 0.6028i 1.4827 + 0.2920i 0.3547 + 0.6149i x1 1.6023 + 0.4387i 0.2077 + 0.6584i 1.2563 + 0.8411i 0.1581 + 0.6842i x2 0.8753 + 1.0881i 0.1711 + 0.3028i 1.0211 + 0.2174i 0.1567 + 0.2749i x3 1.0881 + 0.8753i 0.1556 + 0.3035i 0.8798 + 0.5702i 0.1336 + 0.2700i x4 0.2202 + 0.9238i 0.6028 + 0.3345i 0.2920 + 1.4827i 0.6177 + 0.4030i x5 0.2019 + 0.7818i 0.6577 + 0.2084i 0.8410 + 1.2563i 0.7262 + 0.1756i x6 0.3049 + 0.8454i 0.3021 + 0.1711i 0.2174 + 1.0211i 0.3568 + 0.1756i x7 0.2653 + 0.7540i 0.3028 + 0.1556i 0.5702 + 0.8798i 0.3771 + 0.1336i x8 0.7818 + 0.2019i 0.5556 + 0.8922i 0.3040 + 0.1475i 0.5639 + 0.8864i x9 0.9238 + 0.2202i 0.2352 + 1.0190i 0.3028 + 0.1691i 0.1980 + 1.0277i x10 0.7540 + 0.2653i 0.8450 + 1.2619i 0.6855 + 0.1871i 0.8199 + 1.2515i x11 0.8454 + 0.3049i 0.2922 + 1.4894i 0.6126 + 0.3563i 0.2854 + 1.4691i x12 0.2675 + 0.2479i 0.8929 + 0.5549i 0.1475 + 0.3040i 0.8654 + 0.6058i x13 0.2479 + 0.2675i 1.0197 + 0.2359i 0.1691 + 0.3028i 1.0382 + 0.2141i x14 0.2890 + 0.2701i 1.2626 + 0.8457i 0.1871 + 0.6855i 1.2362 + 0.8416i x15 0.2701 + 0.2890i 1.4894 + 0.2922i 0.3563 + 0.6126i 1.4663 + 0.2973i x/Shape R64_10/15 R64_11/15 R64_12/15 E64_13/15 x0 1.4388 + 0.2878i 0.3317 + 0.6970i 1.0854 + 0.5394i 0.4108 + 0.7473i x1 1.2150 + 0.8133i 0.1386 + 0.8824i 0.7353 + 0.4623i 0.1343 + 0.5338i x2 1.0386 + 0.2219i 0.1323 + 0.4437i 1.0474 + 0.1695i 0.1570 + 0.9240i x3 0.8494 + 0.6145i 0.1015 + 0.1372i 0.7243 + 0.1504i 0.1230 + 0.1605i x4 0.2931 + 1.4656i 0.5682 + 0.4500i 1.0693 + 0.9408i 0.6285 + 0.4617i x5 0.8230 + 1.2278i 0.6739 + 0.1435i 0.7092 + 0.8073i 0.3648 + 0.3966i x6 0.2069 + 1.0649i 0.3597 + 0.3401i 1.4261 + 0.2216i 0.6907 + 0.1541i x7 0.5677 + 0.8971i 0.3660 + 0.1204i 0.6106 + 1.1783i 0.3994 + 0.1308i x8 0.4119 + 0.1177i 0.6004 + 0.8922i 0.1392 + 0.4078i 0.7268 + 0.8208i x9 0.3998 + 0.2516i 0.2120 + 1.2253i 0.4262 + 0.4205i 1.0463 + 0.9495i x10 0.7442 + 0.1559i 0.9594 + 1.0714i 0.1407 + 0.1336i 0.1866 + 1.2733i x11 0.5954 + 0.4328i 0.5829 + 1.3995i 0.4265 + 0.1388i 0.5507 + 1.1793i x12 0.1166 + 0.1678i 0.8439 + 0.5675i 0.1388 + 0.7057i 0.9283 + 0.5140i x13 0.1582 + 0.3325i 0.9769 + 0.1959i 0.4197 + 0.7206i 1.2648 + 0.5826i x14 0.1355 + 0.7408i 1.2239 + 0.6760i 0.1682 + 1.0316i 0.9976 + 0.1718i x15 0.3227 + 0.6200i 1.3653 + 0.2323i 0.2287 + 1.3914i 1.3412 + 0.1944i

TABLE 29 x/Shape R64_6/15 R64_7/15 R64_8/15 R64_9/15 x0 0.4387 + 1.6023i 0.3352 + 0.6028i 1.4827 + 0.2920i 0.3547 + 0.6149i x1 1.6023 + 0.4387i 0.2077 + 0.6584i 1.2563 + 0.8411i 0.1581 + 0.6842i x2 0.8753 + 1.0881i 0.1711 + 0.3028i 1.0211 + 0.2174i 0.1567 + 0.2749i x3 1.0881 + 0.8753i 0.1556 + 0.3035i 0.8798 + 0.5702i 0.1336 + 0.2700i x4 0.2202 + 0.9238i 0.6028 + 0.3345i 0.2920 + 1.4827i 0.6177 + 0.4030i x5 0.2019 + 0.7818i 0.6577 + 0.2084i 0.8410 + 1.2563i 0.7262 + 0.1756i x6 0.3049 + 0.8454i 0.3021 + 0.1711i 0.2174 + 1.0211i 0.3568 + 0.1756i x7 0.2653 + 0.7540i 0.3028 + 0.1556i 0.5702 + 0.8798i 0.3771 + 0.1336i x8 0.7818 + 0.2019i 0.5556 + 0.8922i 0.3040 + 0.1475i 0.5639 + 0.8864i x9 0.9238 + 0.2202i 0.2352 + 1.0190i 0.3028 + 0.1691i 0.1980 + 1.0277i x10 0.7540 + 0.2653i 0.8450 + 1.2619i 0.6855 + 0.1871i 0.8199 + 1.2515i x11 0.8454 + 0.3049i 0.2922 + 1.4894i 0.6126 + 0.3563i 0.2854 + 1.4691i x12 0.2675 + 0.2479i 0.8929 + 0.5549i 0.1475 + 0.3040i 0.8654 + 0.6058i x13 0.2479 + 0.2675i 1.0197 + 0.2359i 0.1691 + 0.3028i 1.0382 + 0.2141i x14 0.2890 + 0.2701i 1.2626 + 0.8457i 0.1871 + 0.6855i 1.2362 + 0.8416i x15 0.2701 + 0.2890i 1.4894 + 0.2922i 0.3563 + 0.6126i 1.4663 + 0.2973i x/Shape R64_10/15 R64_11/15 R64_12/15 E64_13/15 x0 1.4388 + 0.2878i 0.3317 + 0.6970i 1.0854 + 0.5394i 0.4108 + 0.7473i x1 1.2150 + 0.8133i 0.1386 + 0.8824i 0.7353 + 0.4623i 0.1343 + 0.5338i x2 1.0386 + 0.2219i 0.1323 + 0.4437i 1.0474 + 0.1695i 0.1570 + 0.9240i x3 0.8494 + 0.6145i 0.1015 + 0.1372i 0.7243 + 0.1504i 0.1230 + 0.1605i x4 0.2931 + 1.4656i 0.5682 + 0.4500i 1.0693 + 0.9408i 0.6285 + 0.4617i x5 0.8230 + 1.2278i 0.6739 + 0.1435i 0.7092 + 0.8073i 0.3648 + 0.3966i x6 0.2069 + 1.0649i 0.3597 + 0.3401i 1.4261 + 0.2216i 0.6907 + 0.1541i x7 0.5677 + 0.8971i 0.3660 + 0.1204i 0.6106 + 1.1783i 0.3994 + 0.1308i x8 0.4119 + 0.1177i 0.6004 + 0.8922i 0.1392 + 0.4078i 0.7268 + 0.8208i x9 0.3998 + 0.2516i 0.2120 + 1.2253i 0.4262 + 0.4205i 1.0463 + 0.9495i x10 0.7442 + 0.1559i 0.9594 + 1.0714i 0.1407 + 0.1336i 0.1866 + 1.2733i x11 0.5954 + 0.4328i 0.5829 + 1.3995i 0.4265 + 0.1388i 0.5507 + 1.1793i x12 0.1166 + 0.1678i 0.8439 + 0.5675i 0.1388 + 0.7057i 0.9283 + 0.5140i x13 0.1582 + 0.3325i 0.9769 + 0.1959i 0.4197 + 0.7206i 1.2648 + 0.5826i x14 0.1355 + 0.7408i 1.2239 + 0.6760i 0.1682 + 1.0316i 0.9976 + 0.1718i x15 0.3227 + 0.6200i 1.3653 + 0.2323i 0.2287 + 1.3914i 1.3412 + 0.1944i

TABLE 30 x/Shape R6/15 R7/15 R8/15 R9/15 x0 0.6800 + 1.6926i 1.2905 + 1.3099i 1.0804 + 1.3788i 1.3231 + 1.1506i x1 0.3911 + 1.3645i 1.0504 + 0.9577i 1.0487 + 0.9862i 0.9851 + 1.2311i x2 0.2191 + 1.7524i 1.5329 + 0.8935i 1.6464 + 0.7428i 1.1439 + 0.8974i x3 0.2274 + 1.4208i 1.1577 + 0.8116i 1.3245 + 0.9414i 0.9343 + 0.9271i x4 0.8678 + 1.2487i 1.7881 + 0.2509i 0.7198 + 1.2427i 1.5398 + 0.7962i x5 0.7275 + 1.1667i 1.4275 + 0.1400i 0.8106 + 1.0040i 0.9092 + 0.5599i x6 0.8747 + 1.0470i 1.4784 + 0.5201i 0.5595 + 1.0317i 1.2222 + 0.6574i x7 0.7930 + 1.0406i 1.3408 + 0.4346i 0.6118 + 0.9722i 0.9579 + 0.6373i x8 0.2098 + 0.9768i 0.7837 + 0.5867i 1.6768 + 0.2002i 0.7748 + 1.5867i x9 0.2241 + 1.0454i 0.8250 + 0.6455i 0.9997 + 0.6844i 0.6876 + 1.2489i x10 0.1858 + 0.9878i 0.8256 + 0.5601i 1.4212 + 0.4769i 0.5992 + 0.9208i x11 0.1901 + 1.0659i 0.8777 + 0.6110i 1.1479 + 0.6312i 0.6796 + 0.9743i x12 0.5547 + 0.8312i 1.0080 + 0.1843i 0.6079 + 0.6566i 0.5836 + 0.5879i x13 0.5479 + 0.8651i 1.0759 + 0.1721i 0.7284 + 0.6957i 0.6915 + 0.5769i x14 0.6073 + 0.8182i 1.0056 + 0.2758i 0.5724 + 0.7031i 0.5858 + 0.7058i x15 0.5955 + 0.8420i 1.0662 + 0.2964i 0.6302 + 0.7259i 0.6868 + 0.6793i x16 1.4070 + 0.1790i 0.8334 + 1.5554i 0.1457 + 1.4010i 1.6118 + 0.1497i x17 1.7227 + 0.2900i 0.8165 + 1.1092i 0.1866 + 1.7346i 0.9511 + 0.1140i x18 1.3246 + 0.2562i 0.6092 + 1.2729i 0.1174 + 1.1035i 1.2970 + 0.1234i x19 1.3636 + 0.3654i 0.6728 + 1.1456i 0.1095 + 1.0132i 1.0266 + 0.1191i x20 1.3708 + 1.2834i 0.3061 + 1.7469i 0.4357 + 1.3636i 1.5831 + 0.4496i x21 1.6701 + 0.8403i 0.1327 + 1.4056i 0.5853 + 1.6820i 0.9328 + 0.3586i x22 1.1614 + 0.7909i 0.3522 + 1.3414i 0.3439 + 1.0689i 1.2796 + 0.3894i x23 1.2241 + 0.7367i 0.2273 + 1.3081i 0.3234 + 0.9962i 1.0188 + 0.3447i x24 0.9769 + 0.1863i 0.5007 + 0.8098i 0.1092 + 0.6174i 0.5940 + 0.1059i x25 0.9452 + 0.2057i 0.5528 + 0.8347i 0.1074 + 0.6307i 0.7215 + 0.1100i x26 1.0100 + 0.2182i 0.4843 + 0.8486i 0.1109 + 0.6996i 0.5863 + 0.1138i x27 0.9795 + 0.2417i 0.5304 + 0.8759i 0.1076 + 0.7345i 0.6909 + 0.1166i x28 0.8241 + 0.4856i 0.1715 + 0.9147i 0.3291 + 0.6264i 0.5843 + 0.3604i x29 0.8232 + 0.4837i 0.1540 + 0.9510i 0.3126 + 0.6373i 0.6970 + 0.3592i x30 0.8799 + 0.5391i 0.1964 + 0.9438i 0.3392 + 0.6999i 0.5808 + 0.3250i x31 0.8796 + 0.5356i 0.1788 + 0.9832i 0.3202 + 0.7282i 0.6678 + 0.3290i x32 0.1376 + 0.3342i 0.3752 + 0.1667i 0.9652 + 0.1066i 0.1406 + 1.6182i x33 0.1383 + 0.3292i 0.3734 + 0.1667i 0.9075 + 0.1666i 0.1272 + 1.2984i x34 0.1363 + 0.3322i 0.3758 + 0.1661i 0.9724 + 0.1171i 0.1211 + 0.9644i x35 0.1370 + 0.3273i 0.3746 + 0.1649i 0.9186 + 0.1752i 0.1220 + 1.0393i x36 0.1655 + 0.3265i 0.4013 + 0.1230i 0.6342 + 0.1372i 0.1124 + 0.6101i x37 0.1656 + 0.3227i 0.4001 + 0.1230i 0.6550 + 0.1495i 0.1177 + 0.6041i x38 0.1634 + 0.3246i 0.4037 + 0.1230i 0.6290 + 0.1393i 0.1136 + 0.7455i x39 0.1636 + 0.3208i 0.4019 + 0.1218i 0.6494 + 0.1504i 0.1185 + 0.7160i x40 0.1779 + 0.6841i 0.6025 + 0.3934i 1.3127 + 0.1240i 0.4324 + 1.5679i x41 0.1828 + 0.6845i 0.5946 + 0.3928i 0.9572 + 0.4344i 0.3984 + 1.2825i x42 0.1745 + 0.6828i 0.6116 + 0.3879i 1.2403 + 0.2631i 0.3766 + 0.9534i x43 0.1793 + 0.6829i 0.6019 + 0.3837i 1.0254 + 0.4130i 0.3668 + 1.0301i x44 0.3547 + 0.6009i 0.7377 + 0.1618i 0.6096 + 0.4214i 0.3667 + 0.5995i x45 0.3593 + 0.6011i 0.7298 + 0.1582i 0.6773 + 0.4284i 0.3328 + 0.5960i x46 0.3576 + 0.5990i 0.7274 + 0.1782i 0.5995 + 0.4102i 0.3687 + 0.7194i x47 0.3624 + 0.5994i 0.7165 + 0.1746i 0.6531 + 0.4101i 0.3373 + 0.6964i x48 0.2697 + 0.1443i 0.1509 + 0.2425i 0.1250 + 0.1153i 0.1065 + 0.1146i x49 0.2704 + 0.1433i 0.1503 + 0.2400i 0.1252 + 0.1158i 0.1145 + 0.1108i x50 0.2644 + 0.1442i 0.1515 + 0.2437i 0.1245 + 0.1152i 0.1053 + 0.1274i x51 0.2650 + 0.1432i 0.1503 + 0.2425i 0.1247 + 0.1156i 0.1134 + 0.1236i x52 0.2763 + 0.1638i 0.1285 + 0.2388i 0.3768 + 0.1244i 0.1111 + 0.3821i x53 0.2768 + 0.1626i 0.1279 + 0.2419i 0.3707 + 0.1237i 0.1186 + 0.3867i x54 0.2715 + 0.1630i 0.1279 + 0.2431i 0.3779 + 0.1260i 0.1080 + 0.3431i x55 0.2719 + 0.1618i 0.1279 + 0.2406i 0.3717 + 0.1252i 0.1177 + 0.3459i x56 0.6488 + 0.1696i 0.3395 + 0.5764i 0.1161 + 0.3693i 0.3644 + 0.1080i x57 0.6462 + 0.1706i 0.3364 + 0.5722i 0.1157 + 0.3645i 0.3262 + 0.1104i x58 0.6456 + 0.1745i 0.3328 + 0.5758i 0.1176 + 0.3469i 0.3681 + 0.1173i x59 0.6431 + 0.1753i 0.3303 + 0.5698i 0.1171 + 0.3424i 0.3289 + 0.1196i x60 0.5854 + 0.3186i 0.1491 + 0.6316i 0.3530 + 0.3899i 0.3665 + 0.3758i x61 0.5862 + 0.3167i 0.1461 + 0.6280i 0.3422 + 0.3808i 0.3310 + 0.3795i x62 0.5864 + 0.3275i 0.1509 + 0.6280i 0.3614 + 0.3755i 0.3672 + 0.3353i x63 0.5872 + 0.3254i 0.1473 + 0.6225i 0.3509 + 0.3656i 0.3336 + 0.3402i x/Shape R10/15 R11/15 R12/15 R13/15 x0 1.6097 + 0.1548i 0.3105 + 0.3382i 1.1014 + 1.1670i 0.3556 + 0.3497i x1 1.5549 + 0.4605i 0.4342 + 0.3360i 0.8557 + 1.2421i 0.3579 + 0.4945i x2 1.3226 + 0.1290i 0.3149 + 0.4829i 1.2957 + 0.8039i 0.5049 + 0.3571i x3 1.2772 + 0.3829i 0.4400 + 0.4807i 1.0881 + 0.8956i 0.5056 + 0.5063i x4 1.2753 + 1.0242i 0.1811 + 0.3375i 0.5795 + 1.2110i 0.2123 + 0.3497i x5 1.4434 + 0.7540i 0.0633 + 0.3404i 0.6637 + 1.4215i 0.2116 + 0.4900i x6 1.0491 + 0.8476i 0.1818 + 0.4851i 0.6930 + 1.0082i 0.0713 + 0.3489i x7 1.1861 + 0.6253i 0.0633 + 0.4815i 0.8849 + 0.9647i 0.0690 + 0.4960i x8 0.9326 + 0.0970i 0.3084 + 0.1971i 1.2063 + 0.5115i 0.3527 + 0.2086i x9 0.8962 + 0.2804i 0.4356 + 0.1993i 1.0059 + 0.4952i 0.3497 + 0.0713i x10 1.1044 + 0.1102i 0.3098 + 0.0676i 1.4171 + 0.5901i 0.4960 + 0.2123i x11 1.0648 + 0.3267i 0.4342 + 0.0691i 1.0466 + 0.6935i 0.4974 + 0.0698i x12 0.7325 + 0.6071i 0.1775 + 0.1985i 0.6639 + 0.6286i 0.2086 + 0.2079i x13 0.8260 + 0.4559i 0.0640 + 0.1978i 0.8353 + 0.5851i 0.2094 + 0.0690i x14 0.8744 + 0.7153i 0.1775 + 0.0676i 0.6879 + 0.8022i 0.0676 + 0.2079i x15 0.9882 + 0.5300i 0.0647 + 0.0669i 0.8634 + 0.7622i 0.0698 + 0.0683i x16 0.1646 + 1.6407i 0.7455 + 0.3411i 0.1213 + 1.4366i 0.3586 + 0.7959i x17 0.4867 + 1.5743i 0.5811 + 0.3396i 0.1077 + 1.2098i 0.3571 + 0.6392i x18 0.1363 + 1.3579i 0.7556 + 0.4669i 0.0651 + 0.9801i 0.5034 + 0.8271i x19 0.4023 + 1.3026i 0.5862 + 0.4756i 0.2009 + 1.0115i 0.5063 + 0.6600i x20 1.0542 + 1.2584i 0.9556 + 0.3280i 0.3764 + 1.4264i 0.2146 + 0.7862i x21 0.7875 + 1.4450i 1.1767 + 0.3091i 0.3237 + 1.2130i 0.2109 + 0.6340i x22 0.8687 + 1.0407i 0.9673 + 0.4720i 0.5205 + 0.9814i 0.0713 + 0.8093i x23 0.6502 + 1.1951i 1.2051 + 0.5135i 0.3615 + 1.0163i 0.0698 + 0.6467i x24 0.0982 + 0.9745i 0.7367 + 0.2015i 0.0715 + 0.6596i 0.2799 + 1.0862i x25 0.2842 + 0.9344i 0.5811 + 0.2015i 0.2116 + 0.6597i 0.2806 + 1.2755i x26 0.1142 + 1.1448i 0.7316 + 0.0669i 0.0729 + 0.8131i 0.4328 + 0.9904i x27 0.3385 + 1.0973i 0.5782 + 0.0669i 0.2158 + 0.8246i 0.4551 + 1.1812i x28 0.6062 + 0.7465i 0.9062 + 0.1971i 0.5036 + 0.6467i 0.2309 + 0.9414i x29 0.4607 + 0.8538i 1.2829 + 0.1185i 0.3526 + 0.6572i 0.1077 + 1.3891i x30 0.7263 + 0.8764i 0.9156 + 0.0735i 0.5185 + 0.8086i 0.0772 + 0.9852i x31 0.5450 + 1.0067i 1.1011 + 0.0735i 0.3593 + 0.8245i 0.0802 + 1.1753i x32 0.2655 + 0.0746i 0.3244 + 0.8044i 1.2545 + 0.1010i 0.8301 + 0.3727i x33 0.2664 + 0.0759i 0.4589 + 0.8218i 1.0676 + 0.0956i 0.8256 + 0.5256i x34 0.4571 + 0.0852i 0.3207 + 0.6415i 1.4782 + 0.1167i 0.6593 + 0.3668i x35 0.4516 + 0.1062i 0.4509 + 0.6371i 0.8981 + 0.0882i 0.6623 + 0.5182i x36 0.2559 + 0.1790i 0.1920 + 0.8196i 0.5518 + 0.0690i 1.0186 + 0.3645i x37 0.2586 + 0.1772i 0.0633 + 0.8167i 0.6903 + 0.0552i 1.0001 + 0.5242i x38 0.3592 + 0.2811i 0.1811 + 0.6371i 0.5742 + 0.1987i 1.1857 + 0.2725i x39 0.3728 + 0.2654i 0.0640 + 0.6415i 0.7374 + 0.1564i 1.3928 + 0.3408i x40 0.7706 + 0.0922i 0.3331 + 1.0669i 1.2378 + 0.3049i 0.8011 + 0.2227i x41 0.7407 + 0.2260i 0.4655 + 1.0087i 1.0518 + 0.3032i 0.7981 + 0.0735i x42 0.6180 + 0.0927i 0.3433 + 1.2865i 1.4584 + 0.3511i 0.6459 + 0.2198i x43 0.6019 + 0.1658i 0.5004 + 1.5062i 0.9107 + 0.2603i 0.6430 + 0.0713i x44 0.6007 + 0.4980i 0.1971 + 1.0051i 0.6321 + 0.4729i 0.9681 + 0.2205i x45 0.6673 + 0.3928i 0.0735 + 1.0298i 0.7880 + 0.4392i 0.9615 + 0.0735i x46 0.4786 + 0.3935i 0.1498 + 1.5018i 0.6045 + 0.3274i 1.3327 + 0.1039i x47 0.5176 + 0.3391i 0.0865 + 1.2553i 0.7629 + 0.2965i 1.1359 + 0.0809i x48 0.0757 + 0.1003i 0.7811 + 0.8080i 0.0596 + 0.0739i 0.8382 + 0.8709i x49 0.0753 + 0.1004i 0.6167 + 0.8153i 0.1767 + 0.0731i 0.8145 + 0.6934i x50 0.0777 + 0.4788i 0.7636 + 0.6255i 0.0612 + 0.2198i 0.6645 + 0.8486i x51 0.0867 + 0.4754i 0.6000 + 0.6327i 0.1815 + 0.2192i 0.6600 + 0.6786i x52 0.1023 + 0.2243i 0.9898 + 0.7680i 0.4218 + 0.0715i 1.1612 + 0.6949i x53 0.1010 + 0.2242i 1.5855 + 0.1498i 0.2978 + 0.0725i 0.9785 + 0.6942i x54 0.1950 + 0.3919i 0.9476 + 0.6175i 0.4337 + 0.2115i 1.3698 + 0.6259i x55 0.1881 + 0.3969i 1.4625 + 0.4015i 0.3057 + 0.2167i 1.2183 + 0.4841i x56 0.0930 + 0.8122i 0.8276 + 1.0225i 0.0667 + 0.5124i 0.7989 + 1.0498i x57 0.2215 + 0.7840i 0.6313 + 1.0364i 0.2008 + 0.5095i 0.4395 + 1.4203i x58 0.0937 + 0.6514i 0.8815 + 1.2865i 0.0625 + 0.3658i 0.6118 + 1.0246i x59 0.1540 + 0.6366i 0.6342 + 1.2705i 0.1899 + 0.3642i 0.6303 + 1.2421i x60 0.4810 + 0.3606i 1.0422 + 0.9593i 0.4818 + 0.4846i 1.0550 + 0.8924i x61 0.3856 + 0.7037i 1.2749 + 0.8538i 0.3380 + 0.5050i 0.8612 + 1.2800i x62 0.3527 + 0.5230i 1.1556 + 1.1847i 0.4571 + 0.3499i 1.2696 + 0.8969i x63 0.3100 + 0.5559i 1.4771 + 0.6742i 0.3216 + 0.3599i 1.0342 + 1.1181i

Table 26 indicates non-uniform QPSK, table 27 indicates non-uniform 16-QAM, Tables 28 and 29 indicate non-uniform 64-QAM, and table 30 indicates non-uniform 256-QAM.

Referring to these tables, the constellation point of the first quadrant may be defined with reference to tables 26 to 30, and the constellation points in the other three quadrants may be defined in the above-described method.

However, this is merely an example and the modulator 130 may map the output bits outputted from the demultiplexer (not shown) onto the constellation points in various methods.

The interleaving is performed in the above-described method for the following reasons.

Specifically, when the LDPC codeword bits are mapped onto the modulation symbol, the bits may have different reliability (that is, receiving performance or receiving probability) according to where the bits are mapped onto in the modulation symbol. The LDPC codeword bits may have different codeword characteristics according to the configuration of a parity check matrix. That is, the LDPC codeword bits may have different codeword characteristics according to the number of 1 existing in the column of the parity check matrix, that is, the column degree.

Accordingly, the interleaver 120 may interleave to map the LDPC codeword bits having a specific codeword characteristic onto specific bits in the modulation symbol by considering both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol.

For example, when the LDPC codeword formed of bit groups X₀ to X₁₇₉ is group-interleaved based on Equation 21 and Table 11, the group interleaver 122 may output the bit groups in the order of X₅₅, X₁₄₆, X₈₃, . . . , X₁₃₂, X₁₃₅.

In this case, when the modulation method is 16-QAM, the number of columns of the block interleaver 124 is four (4) and each column may be formed of 16200 rows.

Accordingly, from among the 180 groups constituting the LDPC codeword, 45 bit groups (X₅₅, X₁₄₆, X₈₃, X₅₂, X₆₂, X₁₇₆, X₁₆₀, X₆₈, X₅₃, X₅₆, X₈₁, X₉₇, X₇₉, X₁₁₃, X₁₆₃, X₆₁, X₅₈, X₆₉, X₁₃₃, X₁₀₈, X₆₆, X₇₁, X₈₆, X₁₄₄, X₅₇, X₆₇, X₁₁₆, X₅₉, X₇₀, X₁₅₆, X₁₇₂, X₆₅, X₁₄₉, X₁₅₅, X₈₂, X₁₃₈, X₁₃₆, X₁₄₁, X₁₁₁, X₉₆, X₁₇₀, X₉₀, X₁₄₀, X₆₄, X₁₅₉) may be inputted to the first column of the block interleaver 124, 45 bit groups (X₁₅, X₁₄, X₃₇, X₅₄, X₄₄, X₆₃, X₄₃, X₁₈, X₄₇, X₇, X₂₅, X₃₄, X₂₉, X₃₀, X₂₆, X₃₉, X₁₆, X₄₁, X₄₅, X₃₆, X₀, X₂₃, X₃₂, X₂₈, X₂₇, X₃₈, X₄₈, X₃₃, X₂₂, X₄₉, X₅₁, X₆₀, X₄₆, X₂₁, X₄, X₃, X₂₀, X₁₃, X₅₀, X₃₅, X₂₄, X₄₀, X₁₇, X₄₂, X₆) may be inputted to the second column of the block interleaver 124, 45 bit groups (X₁₁₂, X₉₃, X₁₂₇, X₁₀₁, X₉₄, X₁₁₅, X₁₀₅, X₃₁, X₁₉, X₁₇₇, X₇₄, X₁₀, X₁₄₅, X₁₆₂, X₁₀₂, X₁₂₀, X₁₂₆, X₉₅, X₇₃, X₁₅₂, X₁₂₉, X₁₇₄, X₁₂₅, X₇₂, X₁₂₈, X₇₈, X₁₇₁, X₈, X₁₄₂, X₁₇₈, X₁₅₄, X₈₅, X₁₀₇, X₇₅, X₁₂, X₉, X₁₅₁, X₇₇, X₁₁₇, X₁₀₉, X₈₀, X₁₀₆, X₁₃₄, X₉₈, X₁) may be inputted to the third column of the block interleaver 124, and 45 bit groups (X₁₂₂, X₁₇₃, X₁₆₁, X₁₅₀, X₁₁₀, X₁₇₅, X₁₆₆, X₁₃₁, X₁₁₉, X₁₀₃, X₁₃₉, X₁₄₈, X₁₅₇, X₁₁₄, X₁₄₇, X₈₇, X₁₅₈, X₁₂₁, X₁₆₄, X₁₀₄, X₈₉, X₁₇₉, X₁₂₃, X₁₁₈, X₉₉, X₈₈, X₁₁, X₉₂, X₁₆₅, X₈₄, X₁₆₈, X₁₂₄, X₁₆₉, X₂, X₁₃₀, X₁₆₇, X₁₅₃, X₁₃₇, X₁₄₃, X₉₁, X₁₀₀, X₅, X₇₆, X₁₃₂, X₁₃₅) may be inputted to the fourth column of the block interleaver 124.

In addition, the block interleaver 124 may output the bits inputted to the 1^(st) row to the last row of each column serially, and the bits outputted from the block interleaver 124 may be inputted to the modulator 130 serially. In this case, the demultiplexer (not shown) may be omitted or the bits may be outputted serially without changing the order of bits inputted to the demultiplexer (not shown). Accordingly, the bits included in each of the bit groups X₅₅, X₁₅, X₁₁₂, and X₁₂₂ may constitute the modulation symbol.

When the modulation method is 64-QAM, the number of columns of the block interleaver 124 is six (6) and each column may be formed of 10800 rows.

Accordingly, from among the 180 groups constituting the LDPC codeword, 30 bit groups (X₅₅, X₁₄₆, X₈₃, X₅₂, X₆₂, X₁₇₆, X₁₆₀, X₆₈, X₅₃, X₅₆, X₈₁, X₉₇, X₇₉, X₁₁₃, X₁₆₃, X₆₁, X₅₈, X₆₉, X₁₃₃, X₁₀₈, X₆₆, X₇₁, X₈₆, X₁₄₄, X₅₇, X₆₇, X₁₁₆, X₅₉, X₇₀, X₁₅₆) may be inputted to the first column of the block interleaver 124, 30 bit groups (X₁₇₂, X₆₅, X₁₄₉, X₁₅₅, X₈₂, X₁₃₈, X₁₃₆, X₁₄₁, X₁₁₁, X₉₆, X₁₇₀, X₉₀, X₁₄₀, X₆₄, X₁₅₉, X₁₅, X₁₄, X₃₇, X₅₄, X₄₄, X₆₃, X₄₃, X₁₈, X₄₇, X₇, X₂₅, X₃₄, X₂₉, X₃₀, X₂₆) may be inputted to the second column of the block interleaver 124, 30 bit groups (X₃₉, X₁₆, X₄₁, X₄₅, X₃₆, X₀, X₂₃, X₃₂, X₂₈, X₂₇, X₃₈, X₄₈, X₃₃, X₂₂, X₄₉, X₅₁, X₆₀, X₄₆, X₂₁, X₄, X₃, X₂₀, X₁₃, X₅₀, X₃₅, X₂₄, X₄₀, X₁₇, X₄₂, X₆) may be inputted to the third column of the block interleaver 124, 30 bit groups (X₁₁₂, X₉₃, X₁₂₇, X₁₀₁, X₉₄, X₁₁₅, X₁₀₅, X₃₁, X₁₉, X₁₇₇, X₇₄, X₁₀, X₁₄₅, X₁₆₂, X₁₀₂, X₁₂₀, X₁₂₆, X₉₅, X₇₃, X₁₅₂, X₁₂₉, X₁₇₄, X₁₂₅, X₇₂, X₁₂₈, X₇₈, X₁₇₁, X₈, X₁₄₂, X₁₇₈) may be inputted to the fourth column of the block interleaver 124, 30 bit groups (X₁₅₄, X₈₅, X₁₀₇, X₇₅, X₁₂, X₉, X₁₅₁, X₇₇, X₁₁₇, X₁₀₉, X₈₀, X₁₀₆, X₁₃₄, X₉₈, X₁, X₁₂₂, X₁₇₃, X₁₆₁, X₁₅₀, X₁₁₀, X₁₇₅, X₁₆₆, X₁₃₁, X₁₁₉, X₁₀₃, X₁₃₉, X₁₄₈, X₁₅₇, X₁₁₄, X₁₄₇) may be inputted to the fifth column of the block interleaver 124, and 30 bit groups (X₈₇, X₁₅₈, X₁₂₁, X₁₆₄, X₁₀₄, X₈₉, X₁₇₉, X₁₂₃, X₁₁₈, X₉₉, X₈₈, X₁₁, X₉₂, X₁₆₅, X₈₄, X₁₆₈, X₁₂₄, X₁₆₉, X₂, X₁₃₀, X₁₆₇, X₁₅₃, X₁₃₇, X₁₄₃, X₉₁, X₁₀₀, X₅, X₇₆, X₁₃₂, X₁₃₅) may be inputted to the sixth column of the block interleaver 124.

In addition, the block interleaver 124 may output the bits inputted to the 1^(st) row to the last row of each column serially, and the bits outputted from the block interleaver 124 may be inputted to the modulator 130 serially. In this case, the demultiplexer (not shown) may be omitted or the bits may be outputted serially without changing the order of bits inputted to the demultiplexer (not shown). Accordingly, the bits included in each of the bit groups X₅₅, X₁₇₂, X₃₉, X₁₁₂, X₁₅₄, and X₈₇ may constitute the modulation symbol.

As described above, since a specific bit is mapped onto a specific bit in a modulation symbol through interleaving, a receiver side can achieve high receiving performance and high decoding performance.

That is, when LDPC codeword bits of high decoding performance are mapped onto high reliability bits from among bits of each modulation symbol, the receiver side may show high decoding performance, but there is a problem that the LDPC codeword bits of the high decoding performance may not be received. In addition, when the LDPC codeword bits of high decoding performance are mapped onto low reliability bits from among the bits of the modulation symbol, initial receiving performance is excellent, and thus, overall performance is also excellent. However, when many bits showing poor decoding performance are received, error propagation may occur.

Accordingly, when LDPC codeword bits are mapped onto modulation symbols, an LDPC codeword bit having a specific codeword characteristic is mapped onto a specific bit of a modulation symbol by considering both codeword characteristics of the LDPC codeword bits and reliability of the bits of the modulation symbol, and is transmitted to the receiver side. Accordingly, the receiver side can achieve high receiving performance and decoding performance.

Hereinafter, a method for determining π(j), which is a parameter used for group interleaving, according to various exemplary embodiments, will be explained.

According to an exemplary embodiment, when the length of the LDPC codeword is 64800, the size of the bit group is determined to be 360 and thus 180 bit groups exist. In addition, there may be 180! possible interleaving patterns (Herein, factorial means A!=A×(A−1)× . . . ×2×1) regarding an integer A.

In this case, since a reliability level between the bits constituting a modulation symbol may be the same according to a modulationorder, many number of interleaving patterns may be regarded as the same interleaving operation when theoretical performance is considered. For example, when an MSB bit of the X-axis (or rear part-axis) and an MSB bit the Y-axis (or imaginary part-axis) of a certain modulation symbol have the same theoretical reliability, the same theoretical performance can be achieved regardless of the way how specific bits are interleaved to be mapped onto the two MSB bits.

However, such a theoretical prediction may become incorrect as a real channel environment is established. For example, in the case of the QPSK modulation method, two bits of a symbol in a part of a symmetric channel like an additive white Gaussian noise (AWGN) channel theoretically have the same reliability. Therefore, there should be no difference in the performance theoretically when any interleaving method is used. However, in a real channel environment, the performance may be different depending on the interleaving method. In the case of a well-known Rayleigh channel which is not a real channel, the performance of QPSK greatly depends on the interleaving method and thus the performance can be predicted somewhat only by the reliability between bits of a symbol according to a modulation method. However, there should be a limit to predicting the performance.

In addition, since code performance by interleaving may be greatly changed according to a channel which evaluates performance, channels should be always considered to drive an interleaving pattern. For example, a good interleaving pattern in the AWGN channel may be not good in the Rayleigh channel. If a channel environment where a given system is used is closer to the Rayleigh channel, an interleaving pattern which is better in the Rayleigh channel than in the AWGN channel may be selected.

As such, not only a specific channel environment but also various channel environments considered in a system should be considered in order to derive a good interleaving pattern. In addition, since there is a limit to predicting real performance only by theoretical performance prediction, the performance should be evaluated by directly conducting computation experiments and then the interleaving pattern should be finally determined.

However, since there are so many number of possible interleaving patterns to be applied (for example, 180!), reducing the number of interleaving patterns used to predict and test performance is an important factor in designing a high performance interleaver.

Therefore, the interleaver is designed through the following steps according to an exemplary embodiment.

1) Channels C₁, C₂, . . . , C_(k) to be considered by a system are determined.

2) A certain interleaver pattern is generated.

3) A theoretical performance value is predicted by applying the interleaver generated in step 2) to each of the channels determined in step 1). There are various methods for predicting a theoretical performance value, but a well-known noise threshold determining method like density evolution analysis is used according to an exemplary embodiment. The noise threshold recited herein refers to a value that can be expressed by a minimum necessary signal-to-noise ratio (SNR) capable of error-free transmission on the assumption that a cycle-free characteristic is satisfied when the length of a code is infinite and the code is expressed by the Tanner graph. The density evolution analysis may be implemented in various ways, but is not the subject matter of the inventive concept and thus a detailed description thereof is omitted.

4) When noise thresholds for the channels are expressed as TH₁[i], TH₂[i], . . . , TH_(k)[i] for the i-th generated interleaver, a final determination threshold value may be defined as follows:

TH[i]=W ₁ ×TH ₁ [i]+W ₂ ×TH ₂ [i]+ . . . +W _(k) ×TH _(k) [i],

where W ₁ +W ₂ + . . . +W _(k)=1,W ₁ ,W ₂ , . . . ,W _(k)>0

Here, W₁, W₂, . . . , W_(k) are adjusted according to importance of the channels. That is, W₁, W₂, . . . , W_(k) are adjusted to a larger value in a more important channel and W₁, W₂, . . . , W_(k) are adjusted to a smaller value in a less important channel (for example, if the weight values of AWGN and Rayleigh channels are W_(i) and W₂, respectively, W₁ may be set to 0.25 and W₂ may be set to 0.75 when one of the channels is determined to be more important.).

5) B number of interleaver patterns are selected in an ascending order of TH[i] values from among the tested interleaver patterns and are directly tested by conducting performance computation experiments. An FER level for the test is determined as 10̂−3 (for example, B=100).

6) D number of best interleaver patterns are selected from among the B number of interleaver patterns tested in step 5) (for example, D=5).

In general, an interleaver pattern which has a great SNR gain in the area of FER=10̂−3 may be selected as a good performance interleaver in step of 5). However, according to an exemplary embodiment, as shown in FIG. 34, performance of FER required in the system based on the result of real computation experiments for the area of FER=10̂−3 may be predicted through extrapolation, and then an interleaver pattern having good performance in comparison with the expected performance in the FER required in the system may be determined as a good interleaver pattern. According to an exemplary embodiment, the extrapolation based on a linear function may be applied. However, various extrapolation methods may be applied. FIG. 34 illustrates an example of performance extrapolation predicted by the result of computation experiments.

7) The D number of interleaver patterns selected in step 6) are tested by conducting performance computation experiments in each channel. Herein, the FER level for testing is selected as FER required in the system (for example, FER=10̂−6)

8) When an error floor is not observed after the computation experiments, an interleaving pattern having the greatest SNR gain is determined as a final interleaving pattern.

FIG. 35 is a view schematically showing a process of determining B number of interleaver patterns in the steps 2), 3), 4), and 5) of the above-described method for determining the interleaving pattern in the case of AWGN and Rayleigh channels for example.

Referring to FIG. 35, necessary variables i, j, and etc. are initialized in operation S1701, and a noise threshold for the AWGN channel TH1[i] and a noise threshold for the Rayleigh channel TH2[i] are calculated in operation S1702. Then, a final determination noise threshold TH[i] defined in step 4) is calculated in operation S1703, and is compared with a previously calculated final determination noise threshold TH[i−1] in operation S1704. When the final determination noise threshold TH[i] is smaller than the previously calculated final determination noise threshold TH[i−1], TH_S[i] is replaced with the TH[i] and is sotred in operation S1706. Next, i, j values increase by 1 in operation S1707 and this process is repeated until the i value exceeds A which is pre-defined in operation S1708. In this case, A is the total number of interleaver patterns to be tested in steps 2), 3), 4), and 5) and A is typically determined to be greater than or equal to 10000. When all operations described above are completed, interleaver patterns corresponding to TH_S[0], TH_S[1], . . . , TH_S[B−1] which are stored in a descending order of final noise thresholds values in operation S1709.

Hereinbelow, the group interleaver design will be described in greater detail.

Meanwhile, as described above, in that each of bit groups constituting the LDPC codeword correspond to each column group of the parity check matrix, a degree of each column group has an effect on decoding performance of the LDPC codeword.

For example, that a degree of column groups is relatively high indicates that there are relatively larger number of parity check equations which are related to bit groups corresponding to column groups, the bit groups which correspond to column groups having a relatively high degree within a parity check matrix formed of a plurality of column groups may have a greater effect on decoding performance of the LDPC codeword rather than bit groups which correspond to column groups having a relatively low degree. In other words, if column groups having a relatively high degree are not mapped appropriately, the performance of the LDPC codeword will be substantially degraded.

Therefore, the group interleaver may be designed such that a bit group(s) having the highest degree, from among the bit groups constituting the LDPC codeword, is interleaved according to the π(j) and mapped to a specific bit of the modulation symbol (or transmission symbol), and the other bit groups not having the highest degree is randomly mapped to the modulatoin symbol. Under this condition, by observing actual BER/FER performance, the case where the performance of the LDPC codeword is substantially degraded may be avoided.

Hereinbelow, a case where the encoder 110 performs LDPC encoding by using the code rate 8/15 to generate an LDPC codeword having the length of 64800, and constitutes a modulation symbol by using the non-uniform 64-QAM (or 64-NUC) will be described in a greater detail.

In this case, the encoder 110 may perform LDPC encoding based on the parity check matrix comprising the information word submatrix defined by Table 5 and the parity submatrix having a dual diagonal configuration.

Accordingly, the parity check matrix is formed of 180 column groups, and from among the 180 column groups, 20 column groups have the degree of 19, 16 column groups have the degree of 4, 60 column groups have the degree of 3, and 84 column groups have the degree of 2.

Therefore, with respect to only 20 column groups of which the degree is 19, from among the 180 column groups, several π(j) for the 20 column groups may be generated to satisfy a predetermined condition in the group interleaver design, and π(j) for the other column groups may be remain as a blank. The bit groups which correspond to the other column groups may be set to be mapped randomly onto bits constituting a modulation symbol. Then, π(j) for 20 column groups having the most excellent performance is selected by observing actual BER/FER performance regarding a specific SNR value. By fixing a part of π(j), i.e. π(j) for 20 column groups selected as described above, substantial degradation of the performance of the LDPC codeword may be avoided.

Meanwhile, Table 31 may be presented below Table 31-1.

In case of Table 31, Equation 21 may be expressed as Y₃₅=X_(π(35))=X₄, Y₄₂=X_(π(42))=X₈, Y₄₄=X_(π(44))=X₆, . . . , Y₁₄₀=X_(π(140))=X₇, Y₁₄₆=X_(π(146))=X₁₀, Y₁₅₇=X_(π(157))=X₁₅.

That is, the group interleaver 122 may rearrange the order of the plurality of bit groups by changing the 4^(th) bit group to the 35^(th) bit group, the 8^(th) bit group to the 42^(nd) bit group, the 6^(th) bit group to the 44^(th) bit group, . . . , the 7^(th) bit group to the 140^(th) bit group, the 10^(th) bit group to the 146^(th) bit group, and the 15^(th) bit group to the 157^(th) bit group, and by rearranging randomly the other bit groups.

In a case where some bit groups are already fixed, the aforementioned feature is applied in the same manner. In other words, bit groups which correspond to column groups having a relatively high degree from among the other bit groups which are not fixed may have a greater effect on decoding performance of the LDPC codeword than bit groups which correspond to column groups having a relatively low degree. That is, even in the case where degradation of the performance of the LDPC codeword is prevented by fixing the bit groups having the highest degree, the performance of the LDPC codeword may vary according to a method of mapping the other bit groups. Accordingly, a method of mapping bit groups having the next highest degree needs to be selected appropriately, to avoid the case where the performance is relatively poor.

Therefore, in a case where bit groups having the highest degree are already fixed, bit groups having the next highest degree, from among the bit groups constituting the LDPC codeword, may be interleaved according to the π(j) and mapped to a specific bit of a modulation symbol, and the other bit groups may be randomly mapped. Under this condition, by observing actual BER/FER performance, the case where the performance of the LDPC codeword is substantially degraded may be avoided.

Hereinbelow, a case where the encoder 110 performs LDPC encoding by using the code rate 8/15 to generate an LDPC codeword having the length of 64800, and constitutes a modulation symbol by using the non-uniform 64-QAM (or 64-NUC) will be described in a greater detail.

In this case, the encoder 110 may perform LDPC encoding based on the parity check matrix comprising the information word submatrix defined by Table 5 and the parity submatrix having a dual diagonal configuration.

Accordingly, the parity check matrix is formed of 180 column groups, and from among the 180 column groups, 20 column groups have the degree of 19, 16 column groups have the degree of 4, 60 column groups have the degree of 3, and 84 column groups have the degree of 2.

Therefore, in a case where 20 column groups of which the degree is 19 are already fixed as in Table 31, with respect to only 16 column groups of which the degree is 4, from among the other 160 column groups, several π(j) for the 16 column groups may be generated to satisfy a predetermined condition in a group interleaver design, and π(j) for the other column groups may be remain as a blank. The bit groups which correspond to the remaining column groups may be set to be mapped randomly onto bits constituting a modulation symbol. Then, π(j) for 16 column groups having the most excellent performance is selected by observing actual BER/FER performance regarding a specific SNR value. By fixing a part of π(j), i.e. π(j) for 16 column groups selected as described above, substantial degradation of the performance of the LDPC codeword may be avoided.

Meanwhile, Table 33 may be presented below Table 33-1

In case of Table 33, Equation 21 may be expressed as Y₃₅=X_(π(35))=X₄, Y₄₂=X_(π(42))=X₈, Y₄₄=X_(π(44))=X₆, . . . , Y₁₄₀=X_(π(140))=X₇, Y₁₄₆=X_(π(146))=X₁₀, Y₁₅₇=X_(π(157))=X₁₅.

That is, the group interleaver 122 may rearrange the order of the plurality of bit groups by changing the 4^(th) bit group to the 35^(th) bit group, the 8^(th) bit group to the 42^(nd) bit group, the 6^(th) bit group to the 44^(th) bit group, . . . , the 7^(th) bit group to the 140^(th) bit group, the 10^(th) bit group to the 146^(th) bit group, and the 15^(th) bit group to the 157^(th) bit group, and by rearranging randomly the other bit groups.

In a case where some bit groups among the plurality of bit groups constituting the LDPC codeword are already fixed, a bit group(s) having the highest degree among the other bit groups, may be interleaved according to the π(j) and mapped to a specific bit of a modulation symbol, and the other bit groups may be randomly mapped. Under this condition, by observing actual BER/FER performance, the case where the performance of the LDPC codeword is substantially degraded may be avoided.

Hereinbelow, a case where the encoder 110 performs LDPC encoding by using the code rate 8/15 to generate an LDPC codeword having the length of 64800, and constitutes a modulation symbol by using the non-uniform 64-QAM (or 64-NUC) will be described in a greater detail.

In this case, the encoder 110 may perform LDPC encoding based on the parity check matrix comprising the information word submatrix defined by Table 5 and the parity submatrix having a dual diagonal configuration.

Accordingly, the parity check matrix is formed of 180 column groups, and from among the 180 column groups, 20 column groups have the degree of 19, 16 column groups have the degree of 4, 60 column groups have the degree of 3, and 84 column groups have the degree of 2.

Therefore, in a case where 20 column groups of which the degree is 19 and 16 column groups of which the degree is 4 are already fixed as in Table 33, with respect to only 60 column groups of which the degree is 3, from among the other 144 column groups, several π(j) for the 60 column groups may be generated to satisfy a predetermined condition in the first step of a group interleaver design, and π(j) for the other column groups may be remain as a blank. Bit groups which correspond to the other column groups may be set to be mapped randomly onto bits constituting a modulation symbol. Then, π(j) for 60 column groups having the most excellent performance is selected by observing actual BER/FER performance regarding a specific SNR value. By fixing a part of π(j), i.e. π(j) for 60 column groups selected as described above, substantial degradation of the performance of the LDPC codeword may be avoided.

Meanwhile, Table 35 may be presented below Table 35-1.

In case of Table 35, Equation 21 may be expressed as Y₀=X_(π(0))=X₈₆, Y₁=X_(π(1))=X₇₁, Y₂=X_(π(2))=X₅₁, . . . , Y₁₄₆=X_(π(146))=X₁₀, Y₁₅₀=X_(π(150))=X₆₃, Y₁₅₇=X_(π(157))=X₁₅.

That is, the group interleaver 122 may rearrange the order of the plurality of bit groups by changing the 86^(th) bit group to the 0^(th) bit group, the 71^(st) bit group to the 1^(st) bit group, the 51^(st) bit group to the 2^(nd) bit group, . . . , the 10^(th) bit group to the 146^(th) bit group, the 63^(rd) bit group to the 150^(th) bit group, and the 15^(th) bit group to the 157^(th) bit group, and by rearranging randomly the other bit groups.

In the exemplary embodiments described above, the case of performing LDPC encoding based on the coding rate of 8/15 and the parity check matrix formed of the information word submatrix defined by Table 5 and the parity submatrix having a dual diagonal configuration is described, but this is merely exemplary, and even in a case of performing LDPC encoding based on different code rates and different parity check matrix, π(j) can be determined based on the aforementioned method.

According to an aspect of other exemplary embodiment, the case where the encoder 110 performs LDPC encoding by using the code rate 12/15 to generate the LDPC codeword having the length of 64800, and constitutes the modulation symbol by using the non-uniform 64-QAM (or 64-NUC) will be described in a greater detail.

In this case, the encoder 110 may perform LDPC encoding based on the parity check matrix comprising the information word submatrix defined by Table 8 and the parity submatrix having a dual diagonal configuration.

Accordingly, the parity check matrix is composed of 180 column groups, and from among the 180 column groups, 26 column groups have the degree of 14, 118 column groups have the degree of 3, and 36 column groups have the degree of 2.

Therefore, so that, with respect to only 26 column groups of which degree is 14, from among the 180 column groups, several π(j) for the 26 column groups may be generated to satisfy a predetermined condition in the group interleaver design, and π(j) for remaining column groups may be remained as a blank. The bit groups which correspond to the remaining column groups may be set to be mapped randomly onto bits constituting the modulation symbol. Then, π(j) for 26 column groups having the most excellent performance is selected by observing actual BER/FER performance regarding a specific SNR value. By fixing a part of π(j), i.e. π(j) for 26 column groups selected as described above, substantial degradation of the performance of the LDPC codeword may be avoided.

Meanwhile, Table 36 may be presented below Table 36-1.

In case of Table 36, Equation 21 may be expressed as Y₁₉=X_(π(19))=X₁₁, Y₂₄=X_(π(24))=X₁₀, Y₃₃=X_(π(33))=X₀, . . . , Y₁₇₇=X_(π(177))=X₃, Y₁₇₈=X_(π(178))=X₂, Y₁₇₉=X_(π(179))=X₁₄.

That is, the group interleaver 122 may rearrange the order of the plurality of bit groups by changing the 11^(th) bit group to the 19^(th) bit group, the 10^(th) bit group to the 24^(th) bit group, the 0^(th) bit group to the 33^(th) bit group, . . . , the 3^(rd) bit group to the 177^(th) bit group, the 2^(nd) bit group to the 178^(th) bit group, and the 14^(th) bit group to the 179^(th) bit group, and by rearranging randomly the remaining bit groups.

Also, in case of 26 column groups of which degree is 14 are already fixed as in Table 36, so that, with respect to only 118 column groups of which degree is 4, from among the remaining 154 column groups, several π(j) for the 118 column groups may be generated to satisfy a predetermined condition in the group interleaver design, and π(j) for remaining column groups may be remained as a blank. The bit groups which correspond to the remaining column groups may be set to be mapped randomly onto bits constituting the modulation symbol. Then, π(j) for 118 column groups having the most excellent performance is selected by observing actual BER/FER performance regarding a specific SNR value. By fixing a part of π(j), i.e. π(j) for 118 column groups selected as described above, substantial degradation of the performance of the LDPC codeword may be avoided.

Meanwhile, Table 35 may be presented below Table 35-1

In case of Table 38, Equation 21 may be expressed as Y₀=X_(π(0))=X₈₃, Y₁=X_(π(1))=X₉₃, Y₂=X_(π(2))=X₉₄, . . . , Y₁₇₇=X_(π(177))=X₃, Y₁₇₈=X_(π(178))=X₂, Y₁₇₉=X_(π(179))=X₁₄.

That is, the group interleaver 122 may rearrange the order of the plurality of bit groups by changing the 83^(rd) bit group to the 0^(th) bit group, the 93^(rd) bit group to the 1^(st) bit group, the 94^(th) bit group to the 2^(nd) bit group, . . . , the 3^(rd) bit group to the 177^(th) bit group, the 2^(nd) bit group to the 178^(th) bit group, and the 14^(th) bit group to the 179^(th) bit group, and by rearranging randomly the remaining bit groups.

In the exemplary embodiment described above, the case of performing LDPC encoding based on coding rate of 12/15 and the parity check matrix which comprising the information word submatrix defined by Table 8 and the parity submatrix having a dual diagonal configuration is described, but this is merely exemplary, and even in the case of performing LDPC encoding based on different code rates and different parity check matrix, π(j) can be determined based on the aforementioned method.

The transmitting apparatus 100 may transmit the signal mapped onto the constellation to a receiving apparatus (for example, 1200 of FIG. 36). For example, the transmitting apparatus 100 may map the signal mapped onto the constellation onto an Orthogonal Frequency Division Multiplexing (OFDM) frame using OFDM, and may transmit the signal to the receiving apparatus 1200 through an allocated channel.

FIG. 36 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment. Referring to FIG. 36, the receiving apparatus 1200 includes a demodulator 1210, a multiplexer 1220, a deinterleaver 1230 and a decoder 1240.

The demodulator 1210 receives and demodulates a signal transmitted from the transmitting apparatus 100. Specifically, the demodulator 1210 generates a value corresponding to an LDPC codeword by demodulating the received signal, and outputs the value to the multiplexer 1220. In this case, the demodulator 1210 may use a demodulation method corresponding to a modulation method used in the transmitting apparatus 100. To do so, the transmitting apparatus 100 may transmit information regarding the modulation method to the receiving apparatus 1200, or the transmitting apparatus 100 may perform modulation using a pre-defined modulation method between the transmitting apparatus 100 and the receiving apparatus 1200.

The value corresponding to the LDPC codeword may be expressed as a channel value for the received signal. There are various methods for determining the channel value, and for example, a method for determining a Log Likelihood Ratio (LLR) value may be the method for determining the channel value.

The LLR value is a log value for a ratio of the probability that a bit transmitted from the transmitting apparatus 100 is 0 and the probability that the bit is 1. In addition, the LLR value may be a bit value which is determined by a hard decision, or may be a representative value which is determined according to a section to which the probability that the bit transmitted from the transmitting apparatus 100 is 0 or 1 belongs.

The multiplexer 1220 multiplexes the output value of the demodulator 1210 and outputs the value to the deinterleaver 1230.

Specifically, the multiplexer 1220 is an element corresponding to a demultiplexer (not shown) provided in the transmitting apparatus 100, and performs an operation corresponding to the demultiplexer (not shown). That is, the multiplexer 1220 performs an inverse operation of the operation of the demultiplexer (not shown), and performs cell-to-bit conversion with respect to the output value of the demodulator 1210 and outputs the LLR value in the unit of bit. However, when the demultiplexer (not shown) is omitted from the transmitting apparatus 100, the multiplexer 1220 may be omitted from the receiving apparatus 1200.

The information regarding whether the demultiplexing operation is performed or not may be provided by the transmitting apparatus 100, or may be pre-defined between the transmitting apparatus 100 and the receiving apparatus 1200.

The deinterleaver 1230 deinterleaves the output value of the multiplexer 1220 and outputs the values to the decoder 1240.

Specifically, the deinterleaver 1230 is an element corresponding to the interleaver 120 of the transmitting apparatus 100 and performs an operation corresponding to the interleaver 120. That is, the deinterleaver 1230 deinterleaves the LLR value by performing the interleaving operation of the interleaver 120 inversely.

To do so, the deinterleaver 1230 may include a block deinterleaver 1231, a group twist deinterleaver 1232, a group deinterleaver 1233, and a parity deinterleaver 1234 as shown in FIG. 37.

The block deinterleaver 1231 deinterleaves the output of the multiplexer 1220 and outputs the value to the group twist deinterleaver 1232.

Specifically, the block deinterleaver 1231 is an element corresponding to the block interleaver 124 provided in the transmitting apparatus 100 and performs the interleaving operation of the block interleaver 124 inversely.

That is, the block deinterleaver 1231 deinterleaves by writing the LLR value output from the multiplexer 1220 in each row in the row direction and reading each column of the plurality of rows in which the LLR value is written in the column direction by using at least one row formed of the plurality of columns.

In this case, when the block interleaver 124 interleaves by dividing the column into two parts, the block deinterleaver 1231 may deinterleave by dividing the row into two parts.

In addition, when the block interleaver 124 writes and reads in and from the bit group that does not belong to the first part in the row direction, the block deinterleaver 1231 may deinterleave by writing and reading values corresponding to the group that does not belong to the first part in the row direction.

Hereinafter, the block deinterleaver 1231 will be explained with reference to FIG. 38. However, this is merely an example and the block deinterleaver 1231 may be implemented in other methods.

An input LLR v_(i) (0≦i<N_(ldpc)) is written in a r_(i) row and a c_(i) column of the block deinterleaver 1231. Herein, c_(i)=(i mod N_(c)) and

${r_{i} = \left\lfloor \frac{i}{N_{c}} \right\rfloor},$

On the other hand, an output LLR q_(i)(0≦i<N_(c)×N_(r1)) is read from a c_(i) column and a r_(i) row of the first part of the block deinterleaver 1231. Herein,

${c_{i} = \left\lfloor \frac{i}{N_{r\; 1}} \right\rfloor},$

r_(i)=(i mod N_(r1)).

In addition, an output LLR q_(i)(N_(c)×N_(r1)≦i<N_(ldpc)) is read from a c_(i) column and a r_(i) row of the second part. Herein,

${c_{i} = \left\lfloor \frac{\left( {i - {N_{c} \times N_{r\; 1}}} \right)}{N_{r\; 2}} \right\rfloor},$

r_(i)=N_(r1)+{(i−N_(c)×N_(r1)) mode N_(r2)}.

The group twist deinterleaver 1232 deinterleaves the output value of the block deinterleaver 1231 and outputs the value to the group deinterleaver 1233.

Specifically, the group twist deinterleaver 1232 is an element corresponding to the group twist interleaver 123 provided in the transmitting apparatus 100, and may perform the interleaving operation of the group twist interleaver 123 inversely.

That is, the group twist deinterleaver 1232 may rearrange the LLR values of the same bit group by changing the order of the LLR values existing in the same bit group. When the group twist operation is not performed in the transmitting apparatus 100, the group twist deinterleaver 1232 may be omitted.

The group deinterleaver 1233 (or the group-wise deinterleaver) deinterleaves the output value of the group twist deinterleaver 1232 and outputs the value to the parity deinterleaver 1234.

Specifically, the group deinterleaver 1233 is an element corresponding to the group interleaver 122 provided in the transmitting apparatus 100 and may perform the interleaving operation of the group interleaver 122 inversely.

That is, the group deinterleaver 1233 may rearrange the order of the plurality of bit groups in bit group wise. In this case, the group deinterleaver 1233 may rearrange the order of the plurality of bit groups in bit group wise by applying the interleaving method of Tables 11 to 22 inversely according to a length of the LDPC codeword, a modulation method and a code rate.

The parity deinterleaver 1234 performs parity deinterleaving with respect to the output value of the group deinterleaver 1233 and outputs the value to the decoder 1240.

Specifically, the parity deinterleaver 1234 is an element corresponding to the parity interleaver 121 provided in the transmitting apparatus 100 and may perform the interleaving operation of the parity interleaver 121 inversely. That is, the parity deinterleaver 1234 may deinterleave the LLR values corresponding to the parity bits from among the LLR values output from the group deinterleaver 1233. In this case, the parity deinterleaver 1234 may deinterleave the LLR value corresponding to the parity bits inversely to the parity interleaving method of Equation 18.

However, the parity deinterleaver 1234 may be omitted depending on the decoding method and embodiment of the decoder 1240.

Although the deinterleaver 1230 of FIG. 36 includes three (3) or four (4) elements as shown in FIG. 37, operations of the elements may be performed by a single element. For example, when bits each of which belongs to each of bit groups X_(a), X_(b), X_(c), X_(d) constitute a single modulation symbol, the deinterleaver 1230 may deinterleave these bits to locations corresponding to their bit groups based on the received single modulation symbol.

For example, when the code rate is 6/15 and the modulation method is 16-QAM, the group deinterleaver 1233 may perform deinterleaving based on table 11.

In this case, bits each of which belongs to each of bit groups X₅₅, X₁₅, X₁₁₂, X₁₂₂ may constitute a single modulation symbol. Since one bit in each of the bit groups X₅₅, X₁₅, X₁₁₂, X₁₂₂ constitutes a single modulation symbol, the deinterleaver 1230 may map bits onto decoding initial values corresponding to the bit groups X₅₅, X₁₅, X₁₁₂, X₁₂₂ based on the received single modulation symbol.

The decoder 1240 may perform LDPC decoding by using the output value of the deinterleaver 1230. To achieve this, the decoder 1240 may include an LDPC decoder (not shown) to perform the LDPC decoding.

Specifically, the decoder 1240 is an element corresponding to the encoder 110 of the transmitting apparatus 100 and may correct an error by performing the LDPC decoding by using the LLR value output from the deinterleaver 1230.

For example, the decoder 1240 may perform the LDPC decoding in an iterative decoding method based on a sum-product algorithm. The sum-product algorithm is one example of a message passing algorithm, and the message passing algorithm refers to an algorithm which exchanges messages (e.g., LLR value) through an edge on a bipartite graph, calculates an output message from messages input to variable nodes or check nodes, and updates.

The decoder 1240 may use a parity check matrix when performing the LDPC decoding. In this case, the parity check matrix used in the decoding may have the same configuration as that of the parity check matrix used in the encoding of the encoder 110, and this has been described above with reference to FIGS. 20 to 22.

In addition, information on the parity check matrix and information on the code rate, etc. which are used in the LDPC decoding may be pre-stored in the receiving apparatus 1200 or may be provided by the transmitting apparatus 100.

FIG. 39 is a flowchart to illustrate an interleaving method of a transmitting apparatus according to an exemplary embodiment.

First, an LDPC codeword is generated by LDPC encoding based on a parity check matrix (S1410), and the LDPC codeword is interleaved (S1420).

Then, the interleaved LDPC codeword is mapped onto a modulation symbol (S1430). In this case, a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword may be mapped onto a predetermined bit in the modulation symbol.

Each of the plurality of bit groups may be formed of M number of bits, and M may be a common divisor of N_(ldpc) and K_(ldpc) and may be determined to satisfy Q_(ldpc)=(N_(ldpc)−K_(ldpc))/M. Herein, Q_(ldpc) is a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, N_(ldpc) is a length of the LDPC codeword, and K_(ldpc) is a length of information word bits of the LDPC codeword.

Operation S1420 may include interleaving parity bits of the LDPC codeword, dividing the parity-interleaved LDPC codeword by the plurality of bit groups and rearranging the order of the plurality of bit groups in bit group wise, and interleaving the plurality of bit groups the order of which is rearranged.

The order of the plurality of bit groups may be rearranged in bit group wise based on the above-described Equation 21 presented above.

As described above, π(j) in Equation 21 may be determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.

For example, when the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 6/15, π(j) may be defined as in table 11.

In addition, when the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 10/15, π(j) may be defined as in table 14.

In addition, when the LDPC codeword has a length of 64800, the modulation method is 16-QAM, and the code rate is 12/15, π(j) may be defined as in table 15.

In addition, when the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 6/15, π(j) may be defined as in table 17.

In addition, when the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 8/15, π(j) may be defined as in table 18.

In addition, when the LDPC codeword has a length of 64800, the modulation method is 64-QAM, and the code rate is 12/15, π(j) may be defined as in table 21.

The interleaving the plurality of bit groups may include: writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

In addition, the interleaving the plurality of bit groups may include: serially write, in the plurality of columns, at least some bit group which is writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then dividing and writing the other bit groups in an area which remains after the at least some bit group is written in the plurality of columns in bit group wise.

FIG. 40 is a block diagram illustrating a configuration of a receiving apparatus according to an exemplary embodiment.

Referring to FIG. 40, a receiving apparatus 3800 may comprise a controller 3810, an RF receiver 3820, a demodulator 3830 and a service regenerator 3840.

The controller 3810 determines an RF channel and a PLP through which a selected service is transmitted. The RF channel may be identified by a center frequency and a bandwidth, and the PLP may be identified by its PLP ID. A specific service may be transmitted through at least one PLP included in at least one RF channel, for each component constituting the specific service. Hereinafter, for the sake of convenience of explanation, it is assumed that all of data needed to play back one service is transmitted as one PLP which is transmitted through one RF channel. In other words, a service has only one data obtaining path to reproduce the service, and the data obtaining path is identified by an RF channel and a PLP.

The RF receiver 3820 detects an RF signal from an RF channel selected by a controller 3810 and delivers OFDM symbols, which are extracted by performing signal processing on the RF signal, to the demodulator 3830. Herein, the signal processing may include synchronization, channel estimation, equalization, etc. Information required for the signal processing may be a value predetermined by the receiving apparatus 3810 and a transmitter according to use and implementation thereof and included in a predetermined OFDM symbol among the OFDM symbols and then transmitted to the receiving apparatus.

The demodulator 3830 performs signal processing on the OFDM symbols, extracts user packet and delivers the user packet to a service reproducer 3740, and the service reproducer 3840 uses the user packet to reproduce and then output a service selected by a user. Here, a format of the user packet may differ depending on a service implementation method and may be, for example, a TS packet or a IPv4 packet.

FIG. 41 is a block diagram illustrating a demodulator according to an exemplary embodiment.

Referring to FIG. 41, a demodulator 3830 may include a frame demapper 3831, a BICM decoder 3832 for L1 signaling, a controller 3833, a BICM decoder 3834 and an output handler 3835.

The frame demapper 3831 selects a plurality of OFDM cells constituting an FEC block which belongs to a selected PLP in a frame including OFDM symbols, based on control information from the controller 3833, and provides the selected OFDM cells to the BICM decoder 3834. The frame demapper 3831 also selects a plurality of OFDM cells corresponding to at least one FEC block which includes L1 signaling, and delivers the selected OFDM cells to the BICM decoder 3832 for L1 signaling.

The BICM decoder for L1 signaling 3832 performs signal processing on an OFDM cell corresponding to an FEC block which includes L1 signaling, extracts L1 signaling bits and delivers the L1 signaling bits to the controller 3833. In this case, the signal processing may include an operation of extracting an LLR value for decoding an LDPC codeword and a process of using the extracted LLR value to decode the LDPC codeword.

The controller 3833 extracts an L1 signaling table from the L1 signaling bits and uses the L1 signaling table value to control operations of the frame demapper 3831, the BICM decoder 3834 and the output handler 3835. FIG. 41 illustrates that the BICM decoder 3832 for L1 signaling does not use control information of the controller 3833. However, when the L1 signaling has a layer structure similar to the layer structure of the above described L1 pre signaling and L1 post signaling, it is obvious that the BICM decoder 3832 for L1 signaling may be constituted by at least one BICM decoding block, and operation of this BICM decoding block and the frame demapper 3831 may be controlled by L1 signaling information of an upper layer.

The BICM decoder 3834 performs signal processing on the OFDM cells constituting FEC blocks which belong to a selected PLP to extract BBF (Baseband frame)s and delivers the BBFs to the output handler 3835. In this case, the signal processing may include an operation of extracting an LLR value for decoding an LDPC codeword and an operation of using the extracted LLR value to decode the LDPC codeword, which may be performed based on control information output from the controller 3833.

The output handler 3835 performs signal processing on a BBF, extracts a user packet and delivers the extracted user packet to a service reproducer 3840. In this case, the signal processing may be performed based on control information output from the controller 3833.

According to an exemplary embodiment, the output handler 3835 comprises a BBF handler (not shown) which extracts BBP (Baseband packet) from the BBF.

FIG. 42 is a flowchart provided to illustrate an operation of a receiving apparatus from a moment when a user selects a service until the selected service is reproduced, according to an exemplary embodiment.

It is assumed that service information on all services selectable by a user are acquired at an initial scan (S4010) prior to the user's service selection (S4020). Service information may include information on a RF channel and a PLP which transmits data required to reproduce a specific service in a current receiving apparatus. As an example of the service information, program specific information/service information (PSI/SI) in an MPEG2-TS is available, and normally can be achieved through L2 signaling and an upper-layer signaling.

In the initial scan (S4010), comprehensive information on a payload type of PLPs which are transmitted to a specific frequency band. As an example, there may be information on whether every PLP transmitted to the frequency band includes a specific type of data.

When the user selects a service (S4020), the receiving apparatus transforms the selected service to a transmitting frequency and performs RF signaling detection (S4030). In the frequency transforming operation (S4020), the service information may be used.

When an RF signal is detected, the receiving apparatus performs an L1 signaling extracting operation from the detected RF signal (S4050). Then, the receiving apparatus selects a PLP transmitting the selected service, based on the extracted L1 signaling, (S4060) and extracts a BBF from the selected PLP (S4070). In S4060, the service information may be used.

The operation to extract a BBF (S4070) may include an operation of demapping the transmitted frame and selecting OFDM cells included in a PLP, an operation of extracting an LLR value for LDPC coding/decoding from an OFDM cell, and an operation of decoding the LDPC codeword using the extracted LLR value.

The receiving apparatus, using header information of an extracted BBF, extracts a BBP from the BBF (S4080). The receiving apparatus also uses header information of an extracted BBP to extract a user packet from the extracted BBP (S4090). The extracted user packet is used to reproduce the selected service (S4100). In the BBP extraction operation (S4080) and user packet extraction operation (S4090), L1 signaling information extracted in the L1 signaling extraction operation may be used.

According to an exemplary embodiment, the L1 signaling information includes information on types of a user packet transmitted through a corresponding PLP, and information on an operation used to encapsulate the user packet in a BBF. The foregoing information may be used in the user packet extraction operation (S1480). Specifically, this information may be used in an operation of extracting the user packet which is a reverse operation of encapsulation of the user packet in the BBF. In this case, process for extracting user packet from the BBP (restoring null TS packet and inserting TS sync byte) is same as above description.

A non-transitory computer readable medium, which stores a program for performing the interleaving methods according to various exemplary embodiments in sequence, may be provided.

The non-transitory computer readable medium refers to a medium that stores data semi-permanently rather than storing data for a very short time, such as a register, a cache, and a memory, and is readable by an apparatus. Specifically, the above-described various applications or programs may be stored in a non-transitory computer readable medium such as a compact disc (CD), a digital versatile disk (DVD), a hard disk, a Blu-ray disk, a universal serial bus (USB), a memory card, and a read only memory (ROM), and may be provided.

At least one of the components, elements or units represented by a block as illustrated in FIGS. 18, 23, 33, 36 and 37 may be embodied as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to an exemplary embodiment. For example, at least one of these components, elements or units may use a direct circuit structure, such as a memory, processing, logic, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of these components, elements or units may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions. Also, at least one of these components, elements or units may further include a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Further, although a bus is not illustrated in the above block diagrams, communication between the components, elements or units may be performed through the bus. Functional aspects of the above exemplary embodiments may be implemented in algorithms that execute on one or more processors. Furthermore, the components, elements or units represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like.

The foregoing exemplary embodiments and advantages are merely exemplary and are not to be construed as limiting the present inventive concept. The exemplary embodiments can be readily applied to other types of apparatuses. Also, the description of the exemplary embodiments is intended to be illustrative, and not to limit the scope of the inventive concept, and many alternatives, modifications, and variations will be apparent to those skilled in the art. 

What is claimed is:
 1. An interleaving method comprising: encoding input bits to generate parity bits based on a low density parity check (LDPC) code according to a code rate of 8/15 and a code length of 64800; interleaving the parity bits; splitting a codeword comprising the input bits and the interleaved parity bits into a plurality of bit groups; interleaving the plurality of bit groups to provide an interleaved codeword; demultiplexing the interleaved codeword to generate cells; and mapping the cells onto constellation points for 64-QAM, wherein the plurality of bit groups are interleaved based on a following equation: Y _(j) =X _(π(j)) for (0≦j<N _(group)), where X_(j) is a j^(th) bit group among the plurality of bit groups, Y_(j) is a j^(th) bit group among an interleaved plurality of bit groups, N_(group) is a total number of the plurality of bit groups and π(j) denotes a permutation order for the interleaving of the plurality of bit groups, and wherein the π(j) is defined as follows: Order of interleaving π(j) (0 ≦ j < 180) Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Rate 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 8/15 86 71 51 48 89 94 46 81 67 49 80 37 55 61 36 57 52 92 60 82 76 72 44 42 91 62 50 90 40 78 53 58 47 85 70 4 69 43 54 84 93 38 8 64 6 18 77 95 66 59 83 73 17 87 3 75 65 88 79 14 151 117 32 22 123 30 33 162 144 9 121 108 139 142 24 34 20 157 159 138 143 29 140 163 150 175 114 31 12 35 145 28 27 26 16 98 102 103 133 161 21 25 107 153 45 156 23 125 141 56 166 5 1 170 119 68 134 41 74 179 2 129 169 101 99 109 127 168 176 11 0 122 110 113 146 132 165 19 13 39 7 164 106 172 154 149 10 173 131 167 63 147 155 100 171 158 160 15 178 148 152 104 124 177 97 130 118 137 111 126 120 105 115 136 112 96 135 116 174 128


2. The method of claim 1, wherein each of the plurality of bit groups comprises 360 bits.
 3. The method of claim 1, wherein π(j) is determined based on at least one of the code length, a modulation method for the mapping, and the code rate. 